Patent application number | Description | Published |
20080239810 | CELL ARRAY OF SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME - A cell array of a flash memory device includes first and second memory block units, and a voltage generator. Each of the first and second memory block units includes a plurality of memory blocks having a plurality of memory cells. The voltage generator outputs a source voltage, a power supply voltage and a positive bias to the first and second memory block units. The first and second memory block units are connected in parallel through a bit line. | 10-02-2008 |
20080239828 | FLASH MEMORY DEVICE AND ERASE METHOD THEREOF - An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected to a plurality of word lines. A voltage generator is configured to apply an erase voltage to a memory cell block selected for an erase operation, and change a level of the erase voltage if an attempt of the erase operation is not successful. A controller is configured to control the voltage generator to apply a first erase voltage to a memory cell block selected for an erase operation. The first erase voltage corresponds to a previous erase voltage that was used successfully in completing a previous erase operation. The first erase voltage is an erase voltage that is used in a first erase attempt for the erase operation. | 10-02-2008 |
20080247236 | PROGRAM METHOD OF FLASH MEMORY DEVICE - A method for operating a flash memory device includes applying a first program voltage Vp | 10-09-2008 |
20090067248 | PROGRAM METHOD OF FLASH MEMORY DEVICE - In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented. | 03-12-2009 |
20090086545 | Non-Volatile Memory Device and Method of Operating the Same - The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage. | 04-02-2009 |
20090129170 | METHOD OF PROGRAMMING NON-VOLATILE MEMORY DEVICE - A method of programming a non-volatile memory device includes, a bit line, to which a program-inhibited cell is connected, being precharged. After precharging the bit line, a program voltage is applied to a first word line selected for program. When a memory cell connected to a second word line, which is adjacent to the first word line in a direction of a drain select line, is a cell to be programmed, a first pass voltage is applied to the second word line and a second pass voltage is applied to the remaining word lines other than the first and second word lines. | 05-21-2009 |
20090168510 | Method of operating non-volatile memory device - The present invention relates to an operation of a non-volatile memory device. According to a method of operating a non-volatile memory device in accordance with an aspect of the present invention, a first program operation is performed by applying a first program voltage to word lines of memory cells, constituting a memory block. As a result of the first program operation, threshold voltages of the memory cells are firstly measured. A second program operation is performed using a second program voltage, which is increased as much as a difference between a first threshold voltage, that is, a lowest voltage level of the firstly measured threshold voltages and a second threshold voltage, that is, an intermediate voltage level of the firstly measured threshold voltages. The second program operation is repeatedly performed by increasing the second program voltage as much as the difference between the first and second threshold voltages until the lowest threshold voltage becomes higher than a program verify voltage. A pass voltage is then set by reflecting a first voltage level, that is, a difference between a program voltage applied in a last program execution step and the first program voltage. | 07-02-2009 |
20090168538 | Method of Programming Non-Volatile Memory Device - A programming method of a non-volatile memory device may include providing a memory device in which a first word line is preprogrammed in an erase operation of a memory block, pre-programming a second word line according to a program command, and programming the first word line. | 07-02-2009 |
20100002520 | METHOD FOR PROGRAMMING A FLASH MEMORY DEVICE - A method for programming a flash memory device includes applying a program bias to a memory cell of a plurality of memory cells within a memory cell string. Each memory cell string comprises a source select line, a plurality of memory cells and a drain select line. A first pass bias is applied to at least one of the memory cells in a source select line direction relative to the memory cell to which the program bias has been applied. A second pass bias is applied to the memory cells in a drain select line direction relative the memory cell(s) to which the first pass bias has been applied. | 01-07-2010 |
20100072560 | Nonvolatile Memory Device and Method of Manufacturing the same - A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed. | 03-25-2010 |
20100202209 | FLASH MEMORY DEVICE AND PROGRAM METHOD THEREOF - A flash memory device includes a memory cell array on which data is stored, and page buffers that are connected to the memory cells through the bit lines and apply one of the first voltage, second voltage or third voltage between the first and second voltage, to the respective bit line when performing the program. | 08-12-2010 |
20100302862 | Non-volatile Memory Device - The present invention relates to a method of operating a non-volatile memory device. In an aspect of the present invention, the method includes performing a first program operation on the entire memory cells, measuring a first program speed of a reference memory cell, storing the first program speed in a program speed storage unit, repeatedly performing a program/erase operation until before a number of the program/erase operation corresponds to a specific reference value, when the number of the program/erase operation corresponds to the specific reference value, measuring a second program speed of the reference memory cell, calculating a difference between the first program speed and the second program speed, resetting a program start voltage according to the calculated program speed difference, and performing the program/erase operation based on the reset program start voltage. | 12-02-2010 |
20110026330 | PROGRAM METHOD OF FLASH MEMORY DEVICE - In a program method of a flash memory device where memory cells within a string are turned on to electrically connect channel regions, all of the channel regions within a second string are precharged uniformly by applying a ground voltage to a first bit line connected to a first string including to-be-programmed cells and a program-inhibited voltage to a second bit line connected to the second string including program-inhibited cells. If a program operation is executed, channel boosting occurs in the channel regions within the second string including the program-inhibited cells. Accordingly, a channel boosting potential can be increased and a program disturbance phenomenon, in which the threshold voltage of program-inhibited cells is changed, can be prevented. | 02-03-2011 |
20120008361 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes cell gate lines arranged in parallel over a semiconductor substrate, gate lines for select transistors disposed over the semiconductor substrate adjacent to the gate lines of the outermost memory cells, from among the gate lines for the memory cells, and metal lines coupled to the select transistors through contacts. | 01-12-2012 |
20120039127 | FLASH MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A method for operating a flash memory device includes applying a pass voltage to a drain pass word line, a source pass word line, and unselected word lines. The drain pass word line is provided between a drain select line and a word line. The drain pass word line has a structure in the same manner as the word lines. The source pass word line is provided between a source select line and a word line. The source pass word line has a structure in the same manner as the word lines. A program voltage is applied to a selected word line associated with a selected memory cell block. A ground voltage is applied to drain pass word lines and source pass word lines. Word lines associated with unselected memory cell blocks are set to a floating state. | 02-16-2012 |
20120061770 | Nonvolatile Memory Device and Method of Manufacturing the Same - A method of manufacturing a nonvolatile memory device wherein first gate lines and second gate lines are formed over a semiconductor substrate. The first gate lines are spaced-from each other at a first width, the second gate lines are spaced-from each other at a second width, and the first width is wider than the second width. A first ion implantation process of forming first junction regions in the semiconductor substrate between the first gate lines and the second gate lines is performed. A second ion implantation process of forming second junction regions in the respective first junction regions between the first gate lines is then performed. | 03-15-2012 |
20140056092 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device, comprising a memory cell block configured to include word lines disposed between a drain select line and a source select line, a voltage generation circuit configured to generate a compensation voltage when an erase operation is performed, and a row decoder configured to apply the compensation voltage to word lines adjacent to each of the drain select line and the source select line, and apply a word line voltage less than the compensation voltage to the other word lines, and a method of operating the same are disclosed. | 02-27-2014 |
20140347937 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a memory block coupled to word lines and configured to a memory cell including a floating gate, an inter-poly dielectric and a control gate and a peripheral circuit configured to perform an erase loop operation, a program loop operation an electron injection operation of the memory cell, the electron injection operation trapping electrons in the inter-poly dielectric. | 11-27-2014 |
20150049544 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes at least one cell string to include a plurality of dummy memory cells and a plurality of memory cells connected in series between the plurality of dummy memory cells; and the peripheral circuit to control the at least one cell string so that a first type of data represented by a first number of bits is stored in at least one of the dummy memory cells and a second type of data represented by a second number of bits, the second number smaller than the first number, is stored in at least two of the plurality of memory cells. | 02-19-2015 |