| Patent application number | Description | Published |
|---|
| 20090058460 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 03-05-2009 |
| 20090066364 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 03-12-2009 |
| 20090091965 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 04-09-2009 |
| 20090091966 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 04-09-2009 |
| 20090091967 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 04-09-2009 |
| 20090094434 | NONVOLATILE PROGRAMMABLE LOGIC CIRCUIT - A nonvolatile programmable logic circuit using a ferroelectric memory performs a nonvolatile memory function and an operation function without additional memory devices, thereby reducing power consumption. Also, a nonvolatile ferroelectric memory is applied to a FPGA (Field Programmable Gate Array), thereby preventing leakage of internal data and reducing the area of a chip. | 04-09-2009 |
| 20100103720 | BIOSENSOR AND SENSING CELL ARRAY USING THE SAME - A biosensor and a sensing cell array using a biosensor are disclosed. Adjacent materials containing plurality of different ingredients are analyzed to determine the ingredients based on their magnetic susceptibility or dielectric constant. A sensing cell array includes such as a magnetization pair detection sensor including a MTJ (Magnetic Tunnel Junction) or GMR to (Giant Magnetoresistive) device, a magnetoresistive sensor including a MTJ device and a magnetic material (current line), a dielectric constant sensor including a sensing capacitor and a switching device, a magnetization hole detection sensor including a MTJ or GMR device, a current line, a free ferromagnetic layer and a switching device, and a giant magnetoresistive sensor including a GMR device, a switching device and a magnetic material (or forcing wordline). Ingredients of adjacent materials are separated based on electrical characteristics of ingredients by sensing magnetic susceptibility and dielectric constant depending on the sizes of the ingredients. | 04-29-2010 |
| 20100188882 | NONVOLATILE FERROELECTRIC MEMORY AND CONTROL DEVICE USING THE SAME - A nonvolatile ferroelectric memory immediately outputs data stored in a page buffer without performing a cell access operation when a page buffer is accessed. Since a block page address region and a column page address region are arranged in less significant bit region, and a row address region is arranged in more significant bit region, the cell operation is not performed in the access of the page address buffer, thereby improving reliability of the cell and reducing power consumption. | 07-29-2010 |
