| Patent application number | Description | Published |
|---|
| 20080263318 | Timed ports - A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the port and arranged to store a trigger time value; and comparison logic configured to detect whether the current time value matches the trigger time value and, provided that said match is detected, to transfer data between the port and an external environment and alter a ready signal to indicate the transfer. The internal environment comprises: an execution unit for transferring data between the at least one port and the internal environment; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions. The scheduling includes scheduling one or more of said threads for execution in dependence on the ready signal. | 10-23-2008 |
| 20080263330 | Clocked ports - A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute instructions in dependence on a first timing signal and to transfer data between the interior portion and the at least one port in dependence on the first timing signal; and a thread scheduler for scheduling a plurality of threads for execution by the execution unit, each thread comprising a sequence of instructions and the thread scheduler being arranged to schedule the threads in dependence on the first timing signal. The port is arranged to transfer data between the port and an external environment in dependence on a second timing signal, and to alter a ready signal in dependence on the second timing signal to indicate a transfer of data with the external environment. The thread scheduler is configured to schedule one or more associated threads for execution in dependence on the ready signal. | 10-23-2008 |
| 20090013323 | SYNCHRONISATION - The invention provides a processor comprising an execution unit arranged to execute multiple program threads, each thread comprising a sequence of instructions, and a plurality of synchronisers for synchronising threads. Each synchroniser is operable, in response to execution by the execution unit of one or more synchroniser association instructions, to associate with a group of at least two threads. Each synchroniser is also operable, when thus associated, to synchronise the threads of the group by pausing execution of a thread in the group pending a synchronisation point in another thread of that group. | 01-08-2009 |
| 20090013329 | THREAD COMMUNICATIONS - The invention relates to a device comprising a processor, the processor comprising: an execution unit for executing multiple threads, each thread comprising a sequence of instructions; and a plurality of sets of thread registers, each set arranged to store information relating to a respective one of the plurality of threads. The processor also comprises circuitry for establishing channels between thread register sets, the circuitry comprising a plurality of channel terminals and being operable to establish a channel between one of the thread register sets and another thread register set via one of the channel terminals and another channel terminal. Each channel terminal comprises at least one buffer operable to buffer data transferred over a thus established channel and a channel terminal identifier register operable to store an identifier of the other channel terminal via which that channel is established. | 01-08-2009 |
