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Hedberg
Brad Hedberg, Vancouver CA
| Patent application number | Description | Published |
|---|---|---|
| 20100291088 | IL-18 BINDING PROTEINS - The present invention encompasses IL-18 binding proteins, particularly antibodies that bind human interleukin-18 (hIL-18). Specifically, the invention relates to antibodies that are entirely human antibodies. Preferred antibodies have high affinity for hIL-18 and/or that neutralize hIL-18 activity in vitro and in vivo. An antibody of the invention can be a full-length antibody or an antigen-binding portion thereof. Method of making and method of using the antibodies of the invention are also provided. The antibodies, or antibody portions, of the invention are useful for detecting hIL-18 and for inhibiting hIL-18 activity, e.g., in a human subject suffering from a disorder in which hIL-18 activity is detrimental. | 11-18-2010 |
Bradley Hedberg, Burnaby CA
| Patent application number | Description | Published |
|---|---|---|
| 20100260765 | TARGETED BINDING AGENTS DIRECTED TO KDR AND USES THEREOF - 035 - The invention relates to targeted binding agents against KDR and uses of such agents. More specifically, the invention relates to fully human monoclonal antibodies directed to KDR. The described targeted binding agents are useful in the treatment of diseases associated with the activity and/or overproduction of KDR and as diagnostics. | 10-14-2010 |
Christian Hedberg, Dortmund DE
| Patent application number | Description | Published |
|---|---|---|
| 20090156644 | Use of thiazole derivatives and analogues in the treatment of cancer - There is provided a use of a compound of formula (I), wherein X, Y, T, W, A | 06-18-2009 |
David Hedberg, Menlo Park, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20100153815 | Systems and Methods for Decreasing Latency in a Digital Transmission System - Disclosed herein are various embodiments of methods, systems, and apparatus for encoding OFDM packets in a digital communication system. In one exemplary method embodiment, LDPC codewords in an IEEE 802.11 wireless transmission are shortened, decreasing the iterations necessary to insure accurate communications. The codewords are shortened by adding known bits in predetermined locations in the last data symbol of a packet. | 06-17-2010 |
Erik Hedberg, Mercer Island, WA US
| Patent application number | Description | Published |
|---|---|---|
| 20100250730 | AUTOMATED LICENSE RECONCILIATION FOR DEPLOYED APPLICATIONS - Systems, methods, and computer program products are described that perform automated license reconciliation for deployed applications. The applications may be deployed among a plurality of computers. Agents are deployed on respective computers to determine the deployed applications. The agents further determine licensable software product identifiers corresponding to the respective instances of the applications. A license data source module provides entitlements corresponding to respective license agreement(s). A reconciliation module matches the entitlements to the instances of the applications to determine whether the instances of the applications are in compliance with the license agreement(s). | 09-30-2010 |
Erik L. Hedberg, Essex Junction, VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090144492 | STRUCTURE FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A hardware description language (HDL) design structure embodied on a machine-readable data storage medium includes elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further includes a DRAM cache partitioned into a refreshable portion and a non-refreshable portion; and a cache controller configured to assign incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines; wherein cache lines corresponding to data having a usage history below a defined frequency are assigned by the controller to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
| 20090144504 | STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS - A design structure embodied in a machine readable medium used in a design process includes a cache structure having a cache tag array associated with a eDRAM data cache comprising a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, which is smaller than retention time of data in the DRAM data cache; wherein, for any of the cache lines not accessed as a result of a read or a write operation during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid. | 06-04-2009 |
| 20090144507 | APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS - An apparatus for implementing a refreshless, embedded dynamic random access memory (eDRAM) cache device includes a cache structure having a cache tag array associated with a DRAM data cache with a plurality of cache lines, the cache tag array having an address tag, a valid bit and an access bit corresponding to each of the plurality of cache lines; and each access bit configured to indicate whether the corresponding cache line has been accessed as a result of a read or a write operation during a defined assessment period, the defined assessment period being smaller than retention time of data in the DRAM data cache. For any of the cache lines that have not been accessed during the defined assessment period, the individual valid bit associated therewith is set to a logic state that indicates the data in the associated cache line is invalid. | 06-04-2009 |
Erik L. Hedberg, Essex Jct., VT US
| Patent application number | Description | Published |
|---|---|---|
| 20090144506 | METHOD AND SYSTEM FOR IMPLEMENTING DYNAMIC REFRESH PROTOCOLS FOR DRAM BASED CACHE - A method for implementing dynamic refresh protocols for DRAM based cache includes partitioning a DRAM cache into a refreshable portion and a non-refreshable portion, and assigning incoming individual cache lines to one of the refreshable portion and the non-refreshable portion of the cache based on a usage history of the cache lines. Cache lines corresponding to data having a usage history below a defined frequency are assigned to the refreshable portion of the cache, and cache lines corresponding to data having a usage history at or above the defined frequency are assigned to the non-refreshable portion of the cache. | 06-04-2009 |
Jonatan Hedberg, Helsinki FI
| Patent application number | Description | Published |
|---|---|---|
| 20120102401 | METHOD AND APPARATUS FOR PROVIDING TEXT SELECTION - A method for providing selection of a portion of text for touch screen devices may include receiving an indication of a touch gesture in association with a primary word among text being displayed at a touch screen display, causing provision of a selected word indication to indicate inclusion of the primary word as a selected word, causing provision of a pre-selected word indication in relation to at least one secondary word adjacent to the primary word, and enabling expansion of the selected word indication to include the at least one secondary word in response to a touch event selecting the at least one secondary word. A corresponding apparatus and computer program product are also provided. | 04-26-2012 |