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He, Tianjin

Fang He, Tianjin CN

Patent application numberDescriptionPublished
20100236526Common rail electronic control injector - The present invention relates to a common rail electronic control injector, which belongs to the electronic control fuel injection system technology. The injector includes an oil inlet joint, an oil inlet located at outside the oil inlet joint, an electromagnet device, a nozzle body, a needle valve, a valve seat and spray holes, wherein the electromagnet device includes a static core, an armature and a coil, wherein a working gap between the static core and the armature is H, the armature is moveably connected with the needle valve along an axial direction. The present invention further includes a compression spring applying a force to the needle valve, a force mechanism applying a force to the armature, and a block mechanism providing an axial anti-thrust while the armature is reset. The present invention has advantages of lower manufacturing cost, better reliability and smaller driving energy.09-23-2010
20100236527Electronic control common rail DME injection system - A common rail electronic control injection system which uses a DME or a low-viscosity fuel similar with DME to inject into a combustion engine, includes a fuel container, a common rail tube, a high-pressure tube, an electronic control injector, an electronic control unit, a high-pressure pump, a working medium case, a reversing component, and a pressure convertor, wherein the pressure convertor includes at least two working components, each working component is divided into a fuel chamber and a working medium chamber by an dividing element, the dividing element can freely deform or move between the fuel chamber and the working medium chamber by pressure effect. The invention avoids the sealing and abrasion problem in the plunger matching portions which is caused by the low-viscosity fuel so as to greatly improve the lifetime and reliability of system.09-23-2010

Hong-Yun He, Tianjin CN

Patent application numberDescriptionPublished
20090236705APPARATUS AND METHOD FOR SERIES CONNECTION OF TWO DIE OR CHIPS IN SINGLE ELECTRONICS PACKAGE - An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions. Alternatively, it can be by adding an electrically isolating coating on the non-active area of the P-side of a semiconductor device to allow it to be mounted P side down on an electrically conductive substrate or mounting location without modification to the substrate or lead frame.09-24-2009

Jiang He, Tianjin CN

Patent application numberDescriptionPublished
20090185761METHOD OF GENERATING IMAGE FILE - A method of generating an image file may generate corresponding image files from data units in a first storage device of a source. The method of generating an image file includes generating an image file head according to hardware parameter information of the first storage device; partitioning the first storage device into a plurality of data units with the same size; performing a compression process to compress data in the data units, respectively, thereby generating corresponding compressed data blocks; sequentially storing the compressed data blocks in a data area of the image file; creating an index table to use an index value to record start positions of the data units in the first storage device and positions of the compressed data blocks in the data area into the index table; and creating a file foot information to mark a file length of the image file.07-23-2009
20090185762DATA STRUCTURE FOR IMAGE FILE - A data structure for an image file includes an image file head, a data area, an index table, and file tail information. The image file head records hardware parameter information of a storage device and partitions the storage device into a plurality of data units. The data units are compressed to generate corresponding compressed data blocks. The generated compressed data blocks are stored in the data area. The index table uses an index value to record start positions of the data units and positions of the compressed data blocks in the image file into the index table. The file tail information marks a file length of the image file. During network transmission of the image file, a destination may restore the received compressed data blocks to the corresponding positions.07-23-2009

Qingchun He, Tianjin CN

Patent application numberDescriptionPublished
20100248426METHOD OF MAKING CHIP-ON-LEAD PACKAGE - A process for assembling a Chip-On-Lead packaged semiconductor device includes the steps of: mounting and sawing a wafer to provide individual semiconductor dies; performing a first molding operation on a lead frame; depositing epoxy on the lead frame via a screen printing process; attaching one of the singulated dies on the lead frame with the epoxy, where the die attach is done at room temperature; and curing the epoxy in an oven. Throughput improvements may be ascribed to not including a hot die attach process. An optional plasma cleaning step may be performed, which greatly improves wire bonding quality and a second molding quality. In addition, since a first molding operation is performed before the formation of epoxy to avoid the problem of the epoxy hanging in the air, the delamination risk between the epoxy and the die is avoided.09-30-2010
20110065240LEAD FRAME AND METHOD OF FORMING SAME - A lead frame and a method of making a lead frame for a semiconductor package. The lead frame is formed by stamping a lead frame material into a desire configuration. The stamped lead frame is then affixed to a support material. When assembling a semiconductor package using the lead frame, during saw singuation, the saw does not have to cut through much lead frame material. Thus, the saw blade does not wear quickly.03-17-2011
20110165729METHOD OF PACKAGING SEMICONDUCTOR DEVICE - Quad Flat No-Lead packaged devices are manufactured using two singulation operations with two different saw blades of varying widths with the first singulation operation using a wider saw blade than the second singulation operation. Between singulation operations, the exposed portions of the leads are plated with a solderable metal. By performing the second singulation operation within the first cut made by the first singulation, at least half of the exposed metal of the leads remains plated. Thus, better solder joints may be formed, which allows for simpler visual inspection.07-07-2011

Qing Chun He, Tianjin CN

Patent application numberDescriptionPublished
20090111220COATED LEAD FRAME - A lead frame having a coating of organic compounds on its lead fingers prevents tin and flux from contaminating the lead fingers after die attach. The coating is removed prior to wire bonding. The coating allows for reliable second bonds (bond between wires and lead fingers) to be formed, decreasing the likelihood of non-stick and improving wire peel strength.04-30-2009

Xianghui He, Tianjin CN

Patent application numberDescriptionPublished
20090016961Stem Cell Fusion Model of Carcinogenesis - Methods for modeling cancer cell migration, screening drugs for effects on tumor cell migration, and detecting the potential for tumor cell migration relating to the fusion of a bone marrow derived stem cell with a genetically altered cell (FIG. 01-15-2009