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He, AZ
Dongming He, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090065931 | PACKAGED INTEGRATED CIRCUIT AND METHOD OF FORMING THEREOF - Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (μm) to about 65 μm. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 μm to about 25 μm. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate. | 03-12-2009 |
Dongming He, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090115057 | C4 JOINT RELIABILITY - In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump. | 05-07-2009 |
Jianggi He, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090250707 | Multi-chip assembly with optically coupled die - Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed. | 10-08-2009 |
Jiangqi He, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20080316662 | Reducing input capacitance for high speed integrated circuits - An integrated circuit with reduced pad capacitance, having a trench formed in the silicon substrate below the pad to reduce the pad capacitance. In another embodiment, an encapsulated air cavity if formed underneath the pad. Other embodiments are described and claimed. | 12-25-2008 |
| 20090039482 | Package Including a Microprocessor & Fourth Level Cache - A method, apparatus and system with a package including an integrated circuit disposed between die including a microprocessor and a die including a fourth level cache. | 02-12-2009 |
| 20090200681 | Forming Compliant Contact Pads For Semiconductor Packages - In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed. | 08-13-2009 |
| 20100059858 | Integrated capacitors in package-level structures, processes of making same, and systems containing same - An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure. | 03-11-2010 |
| 20110058419 | MULTI-CHIP ASSEMBLY WITH OPTICALLY COUPLED DIE - Disclosed are embodiments of a multi-chip assembly including optically coupled die. The multi-chip assembly may include two opposing substrates, and a number of die are mounted on each of the substrates. At least one die on one of the substrates is in optical communication with at least one opposing die on the other substrate. Other embodiments are described and claimed. | 03-10-2011 |
| 20110175230 | Forming Compliant Contact Pads for Semiconductor Packages - In one embodiment, the present invention includes a semiconductor package having a substrate with a first surface to support a semiconductor die. A second surface of the substrate includes compliant conductive pads to provide electrical connections to the semiconductor die. In this way, improved connection between the semiconductor package and a socket is provided. Other embodiments are described and claimed. | 07-21-2011 |
| 20110239454 | Substrate With Raised Edge Pads - A separable electrical connection may be provided with a landside pad on one of two electrical components to be joined. The landside pad may be made up of two parts, including a flat portion and a raised edge formed on the flat portion. In some embodiments, the raised edge may have a closed geometric shape. Then, a socket contact engaging the junction between the flat portion and the raised edge is prevented from sliding off of the landside pad by the raised edge. In addition, dual areas of electrical connection can be established between both the flat portion and raised edge of the landside pad and the correspondingly shaped pair of portions on the socket. This increases the electrical efficiency of the connection and its security. | 10-06-2011 |
| 20120077357 | SELF REFERENCING PIN - Methods and apparatus relating to self-referencing pins are described. In one embodiment, a pin electrically couples a first agent to a second agent. The pin includes two or more portions that are at least partially separated by an insulator, e.g., to improve crosstalk performance. Other embodiments are also disclosed and claimed. | 03-29-2012 |
Jianqqi He, Gilbert, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090201643 | INTEGRATED MICRO-CHANNELS FOR 3D THROUGH SILICON ARCHITECTURES - Some embodiments of the present invention include apparatuses and methods relating to integrated micro-channels for removing heat from 3D through silicon architectures. | 08-13-2009 |
Jin He, Scottsdale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110120868 | Nanopore and Carbon Nanotube Based DNA Sequencer and a Serial Recognition Sequencer - The present invention is directed to systems, devices and methods for identifying biopolymers, such as strands of DNA, as they pass through a constriction such as a carbon nanotube nanopore. More particularly, the invention is directed to such systems, devices and methods in which a newly translocated portion of the biopolymer forms a temporary electrical circuit between the nanotube nanopore and a second electrode, which may also be a nanotube. Further, the invention is directed to such systems, devices and methods in which the constriction is provided with a functionalized unit which, together with a newly translocated portion of the biopolymer, forms a temporary electrical circuit that can be used to characterize that portion of the biopolymer. | 05-26-2011 |
| 20110168562 | Nanopore and Carbon Nanotube Based DNA Sequencer - The present invention provides a device for analyzing the composition of a heteropolymer comprising a carbon nanotube through which the heteropolymer is driven by electrophoresis. The carbon nanotube also serves as one electrode in a reading circuit. One end of the carbon nanotube is held in close proximity to a second electrode, and each end of the carbon nanotube is functionalized with flexibly-tethered chemical-recognition moieties, such that one will bind one site on the emerging polymer, and the second will bind another site in close proximity, generating an electrical signal between the two electrodes when the circuit is completed by the process of chemical recognition. | 07-14-2011 |
Jin He, Mesa, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20120288948 | CONTROLLED TUNNEL GAP DEVICE FOR SEQUENCING POLYMERS - The invention includes compositions, devices, and methods for analyzing a polymer and/or polymer unit. The polymer may be a homo- or hetero-polymer such as DNA, RNA, a polysaccharide, or a peptide. The device includes electrodes that form a tunnel gap through which the polymer can pass. The electrodes are functionalized with a reagent attached thereto, and the reagent is capable of forming a transient bond to a polymer unit. When the transient bond forms between the reagent and the unit, a detectable signal is generated and used to analyze the polymer. | 11-15-2012 |
Jiping He, Tempe, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100145216 | Neural Interface Assembly and Method For Making and Implanting The Same - An implant assembly for creating a neural interface with a central nervous system having at least one biocompatible intracortical electrode is presented along with a method of making and implanting device. The mechanical, electrical and biological characteristics of the assembly support its use as a reliable long term implant. | 06-10-2010 |
Liyan He, Chandler, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20100292930 | METHODS FOR GENERATING DATABASES AND DATABASES FOR IDENTIFYING POLYMORPHIC GENETIC MARKERS - Processes and methods for creating a database of genomic samples from healthy human donors, methods that use the database to identify and correlate polymorphic genetic markers and other markers with diseases and conditions are provided. | 11-18-2010 |
Mengtao Pete He, Phoenix, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20090178295 | APPARATUS AND METHODS FOR TREATING FABRICS IN A LAUNDRY DRYER - The present teachings provide apparatus and methods for reducing wrinkles in a laundered fabric. In various embodiments, the apparatus includes a dryer and a vapor generator device mounted within the dryer that dispenses a wrinkle reduction composition into the dryer upon a signal from a sensor in the dryer. Furthermore, the present teachings provide methods for delivering a wrinkle reduction composition into laundry dryer. In an exemplary embodiment, a method can include electronically monitoring at least one operating parameter of a laundry dryer to determine when the operating parameter meets a first preset condition, then activating a vapor generator when the first preset condition is met, and dispensing a vapor of a wrinkle reduction composition into the laundry dryer. | 07-16-2009 |
Mengtao Pete He, Scottsdale, AZ US
| Patent application number | Description | Published |
|---|---|---|
| 20110030233 | DRYER DEVICE WITH END OF USE INDICATOR - The invention discloses an end of use indicator (EUI) with a visual cue and a dryer device thereof. The EUI prompts the consumer to refill a cartridge within a device, replace a cartridge within a device, or replace the device itself. In one exemplary embodiment, the present invention teaches a repetitive use, dryer device with an EUI for the treatment of fabrics in a laundry dryer. | 02-10-2011 |
| 20110124544 | CONSUMER PRODUCTS COMPRISING ALGAE DERIVED INGREDIENTS - The present invention discloses bio-based consumer products formulated with at least one algae-derived ingredient that is either directly obtained from algae colonies or derived through standard synthetic organic transformations starting from bioorganic substances of algae origin. | 05-26-2011 |