Patent application number | Description | Published |
20090057821 | REPROGRAMMABLE METAL-TO-METAL ANTIFUSE EMPLOYING CARBON-CONTAINING ANTIFUSE MATERIAL - A reprogrammable metal-to-metal antifuse is disposed between two metal interconnect layers in an integrated circuit. A lower barrier layer is formed from Ti. A lower adhesion-promoting layer is disposed over the lower Ti barrier layer. An antifuse material layer selected from a group comprising at least one of amorphous carbon and amorphous carbon doped with at least one of hydrogen and fluorine is disposed over the lower adhesion-promoting layer. An upper adhesion-promoting layer is disposed over the antifuse material layer. An upper Ti barrier layer is disposed over the upper adhesion-promoting layer. | 03-05-2009 |
20100149873 | PUSH-PULL FPGA CELL - A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate. | 06-17-2010 |
20110018070 | NON-VOLATILE PROGRAMMABLE MEMORY CELL AND ARRAY FOR PROGRAMMABLE LOGIC ARRAY - A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor. | 01-27-2011 |
20110024821 | PUSH-PULL FPGA CELL - A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate. | 02-03-2011 |
20140246644 | Front to Back Resistive Random Access Memory Cells - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 09-04-2014 |
Patent application number | Description | Published |
20080197450 | AMORPHOUS CARBON METAL-TO-METAL ANTIFUSE WITH ADHESION PROMOTING LAYERS - A metal-to-metal antifuse having a lower metal electrode, a lower thin adhesion promoting layer disposed over the lower metal electrode, an amorphous carbon antifuse material layer disposed over the thin adhesion promoting layer, an upper thin adhesion promoting layer disposed over said antifuse material layer, and an upper metal electrode. The thin adhesion promoting layers are about 2 angstroms to 20 angstroms in thickness, and are from a material selected from the group comprising Si | 08-21-2008 |
20110001108 | FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 01-06-2011 |
20110001115 | RESISTIVE RAM DEVICES FOR PROGRAMMABLE LOGIC DEVICES - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 01-06-2011 |
20110001116 | BACK TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 01-06-2011 |
20130221316 | FRONT TO BACK RESISTIVE RANDOM ACCESS MEMORY CELLS - A resistive random access memory device formed on a semiconductor substrate comprises an interlayer dielectric having a via formed therethrough. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A barrier metal liner lines walls of the via. A conductive plug is formed in the via. A first barrier metal layer is formed over the chemical-mechanical-polishing stop layer and in electrical contact with the conductive plug. A dielectric layer is formed over the first barrier metal layer. An ion source layer is formed over the dielectric layer. A dielectric barrier layer is formed over the ion source layer, and includes a via formed therethrough communicating with the ion source layer. A second barrier metal layer is formed over the dielectric barrier layer and in electrical contact with the ion source layer. A metal interconnect layer is formed over the barrier metal layer. | 08-29-2013 |
Patent application number | Description | Published |
20110118189 | NOVEL FORMULATIONS FOR TREATMENT OF MIGRAINE - Systems and methods are described for treating un-met medical needs in migraine and related conditions such as cluster headache. Included are treatments that are both rapid onset and long acting, which include sustained release formulations, and combination products. Also included are treatments for multiple symptoms of migraine, especially headache and nausea and vomiting. Systems that are self contained, portable, prefilled, and simple to self administer at the onset of a migraine attack are disclosed, and preferably include a needle-free injector and a high viscosity formulation, to eliminate such issues as fear of self administration with needles, and needle stick and cross contamination. | 05-19-2011 |
20130231311 | NOVEL FORMULATIONS FOR TREATMENT OF MIGRAINE - Systems and methods are described for treating un-met medical needs in migraine and related conditions such as cluster headache. Included are treatments that are both rapid onset and long acting, which include sustained release formulations, and combination products. Also included are treatments for multiple symptoms of migraine, especially headache and nausea and vomiting. Systems that are self contained, portable, prefilled, and simple to self administer at the onset of a migraine attack are disclosed, and preferably include a needle-free injector and a high viscosity formulation, to eliminate such issues as fear of self administration with needles, and needle stick and cross contamination. | 09-05-2013 |
20140148485 | NOVEL FORMULATIONS FOR TREATMENT OF MIGRANE - Systems and methods are described for treating un-met medical needs in migraine and related conditions such as cluster headache. Included are treatments that are both rapid onset and long acting, which include sustained release formulations, and combination products. Also included are treatments for multiple symptoms of migraine, especially headache and nausea and vomiting. Systems that are self contained, portable, prefilled, and simple to self administer at the onset of a migraine attack are disclosed, and preferably include a needle-free injector and a high viscosity formulation, to eliminate such issues as fear of self administration with needles, and needle stick and cross contamination. | 05-29-2014 |
Patent application number | Description | Published |
20140194431 | PYRIMIDONE DERIVATIVES AND THEIR USE IN THE TREATMENT, AMELIORATION OR PREVENTION OF A VIRAL DISEASE - The present invention relates to a compound having the general formula (I), optionally in the form of a pharmaceutically acceptable salt, solvate, polymorph, codrug, cocrystal, prodrug, tautomer, racemate, enantiomer, or diastereomer or mixture thereof, | 07-10-2014 |
20140194432 | NAPHTHYRIDINONE DERIVATIVES AND THEIR USE IN THE TREATMENT, AMELIORATION OR PREVENTION OF A VIRAL DISEASE - The present invention relates to a compound having the general formula (V), optionally in the form of a pharmaceutically acceptable salt, solvate, polymorph, codrug, cocrystal, prodrug, tautomer, racemate, enantiomer, or diastereomer or mixture thereof, | 07-10-2014 |
20140194476 | PYRIDONE DERIVATIVES AND THEIR USE IN THE TREATMENT, AMELORIATION OR PREVENTION OF A VIRAL DISEASE - The present invention relates to a compound having the general formula (II), optionally in the form of a pharmaceutically acceptable salt, solvate, polymorph, codrug, cocrystal, prodrug, tautomer, racemate, enantiomer, or diastereomer or mixture thereof, | 07-10-2014 |