Hatsch
Anaelle Hatsch, Wittisheim FR
Patent application number | Description | Published |
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20150211036 | GENES AND PROCESSES FOR THE PRODUCTION OF CLAVINE-TYPE ALKALOIDS - Microorganisms and processes for the recombinant manufacture of clavine-type alkaloids such as cycloclavine, festuclavine, agroclavine, chanoclavine and chanoclavine aldehyde, as well as polypeptides, polynucleotides and vectors comprising such polynucleotides which can be applied in a method for the manufacture of clavine-type alkaloids are provided. | 07-30-2015 |
Didier Hatsch, Riom FR
Patent application number | Description | Published |
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20110004410 | DEVICE FOR THE COLLECTION AND PROCESSING OF INFORMATION RELATING TO THE EXPOSURE OF ONE OR MORE PERSONS TO ONE OR MORE PRODUCTS OF CHEMICAL OR BIOLOGICAL ORIGIN AND METHOD FOR THE USE OF SUCH A DEVICE - A device for the collection and processing of information relating to the exposure of one or more persons ( | 01-06-2011 |
Joel Hatsch, Holzkirchen DE
Patent application number | Description | Published |
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20120020145 | Identification Circuit and Method for Generating an Identification Bit - A semiconductor device includes an identification circuit. The identification circuit includes a memory cell which includes a first transistor having a first value of a switching characteristic and a second transistor having a second value of the switching characteristic. The identification circuit is operable to generate a memory-cell-specific identification bit which is dependent on production-dictated differences in the first switching characteristic of the first transistor and the second switching characteristic of the second transistor. The identification circuit further includes a drive circuit for the memory cell. The drive circuit is operable to connect or isolate an upper supply potential and a lower supply potential of the semiconductor device to or from the memory cell independently of one another. | 01-26-2012 |
20120307579 | MEMORY RELIABILITY VERIFICATION TECHNIQUES - Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells. | 12-06-2012 |