Patent application number | Description | Published |
20100110755 | FERROELECTRIC RANDOM ACCESS MEMORY DEVICE - A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on. | 05-06-2010 |
20100124092 | FERROELECTRIC MEMORY DEVICE - According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor. | 05-20-2010 |
20100157650 | FERROELECTRIC MEMORY - A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation. | 06-24-2010 |
20110058403 | FERRO-ELECTRIC RANDOM ACCESS MEMORY APPARATUS - A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout. | 03-10-2011 |
20110063886 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information. | 03-17-2011 |
20120246388 | MEMORY SYSTEM, NONVOLATILE STORAGE DEVICE, CONTROL METHOD, AND MEDIUM - According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid. | 09-27-2012 |
20130159785 | SEMICONDUCTOR STORAGE DEVICE, METHOD FOR CONTROLLING THE SAME AND CONTROL PROGRAM - According to one embodiment, a semiconductor memory stores a program for causing a memory controller to operate in at least one of first and second modes. In the first mode, for each of the blocks, the memory controller autonomously erases and writes data and reads the written data, and determines that the block or the semiconductor storage device is defective when a count of errors in the read data exceeds a correction capability or a threshold. In the second mode, when error correction of read substantial data fails, the memory controller reads the substantial data which failed in the error correction using a read level shifted from the present read level. | 06-20-2013 |
20130159814 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 06-20-2013 |
20130332802 | SEMICONDUCTOR STORAGE DEVICE, NONVOLATILE SEMICONDUCTOR MEMORY TEST METHOD, AND MEDIUM - According to one embodiment, a semiconductor storage device includes a nonvolatile semiconductor memory and a controller. The nonvolatile semiconductor memory includes a firmware area capable of storing firmware used to execute either a normal mode or an autorun test mode and a user area capable of storing user data. The controller reads the firmware from the nonvolatile semiconductor memory and determines whether the firmware has been set in either the normal mode or the autorun test mode. The controller repeats erasing, writing, and reading in each block in the user area using a cell applied voltage higher than a voltage used in a normal mode, and enters a block where an error has occurred as a bad block. | 12-12-2013 |
20140173268 | INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROLLING INFORMATION PROCESSING APPARATUS, NON-TRANSITORY RECORDING MEDIUM STORING CONTROL TOOL, HOST DEVICE, NON-TRANSITORY RECORDING MEDIUM STORING PERFORMANCE EVALUATION TOOL, AND PERFORMANCE EVALUATION METHOD FOR EXTERNAL MEMORY DEVICE - According to the embodiments, a nonvolatile memory device is configured to store a normal operating system, and store a bootloader. A host device is capable of initiating the normal operating system by using the bootloader. The host device is configured to determine whether a first condition is established based on information obtained from the nonvolatile memory device; and rewrite, when determined the first condition is established, the bootloader so that an emergency software is initiated when booting the host device. The emergency software is executed on the host device. The host device is capable of issuing only a read command to the nonvolatile memory device under a control of the emergency software. | 06-19-2014 |
Patent application number | Description | Published |
20110085126 | METHOD OF AND APPARATUS FOR PRODUCING LIQUID CRYSTAL DISPLAY DEVICE - One aspect of the invention provides a liquid crystal display device producing method for irradiating a liquid crystal display substrate, in which plural pixels are formed in a matrix state and liquid crystal is sealed between a TFT substrate and a counter electrode substrate, with light having a predetermined wavelength to orient liquid crystal molecules toward a predetermined direction in a state in which an electric field is applied to each pixel of the liquid crystal display substrate. The method includes the steps of: dipping the liquid crystal display substrate and a lamp in a transparent liquid having resistivity of a predetermined value or more and sufficiently high transmittance to the light in a state in which the liquid crystal display substrate and the lamp face each other; and lighting the lamp to irradiate the liquid crystal display substrate with the light having a predetermined light quantity in a state in which the electric field is applied to each pixel. | 04-14-2011 |
20110244379 | METHOD FOR FORMING CONVEX PATTERN, EXPOSURE APPARATUS AND PHOTOMASK - The present invention is a photomask | 10-06-2011 |
20120236283 | EXPOSURE APPARATUS - Exposure apparatus includes photomasks on which a mask pattern having the same shape as that of an exposure pattern exposed onto a surface of a TFT substrate held on a stage is formed, lens assemblies in which unit lens groups in each of which a plurality of convex lenses are arranged in a normal direction to the photomasks so that same-size erect images of mask patterns formed on the photomasks can be formed on the surface of the TFT substrate are arranged in a plane parallel with the photomasks and the surface of the TFT substrate held on the stage, and moving device that moves the lens assemblies in a plane parallel with the masks and the surface of TFT substrate held on the stage. | 09-20-2012 |
20130230799 | FILM EXPOSURE METHOD - On a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material, a colored firing material, colored light-curable material, or colored ink is applied to at least one of two widthwise side edges to form a side part application coating, which is irradiated with laser light by an alignment mark formation unit to form an alignment mark. The alignment mark is then used to detect film meandering and adjust the positions of masks. This makes it easy to form the alignment mark and detect the alignment mark thus formed and makes it possible to accurately correct for meandering of a film and stably expose the film in the process of continuous exposure of a film where an exposure material coating has been formed in a exposure pattern formation region on a film base material. | 09-05-2013 |
20140168648 | ALIGNMENT DEVICE FOR EXPOSURE DEVICE, AND ALIGNMENT MARK - This alignment device is furnished with an alignment light source for emitting alignment light, and is housed with a camera for example. The alignment light source emits alignment light, doing so, for example, coaxially with respect to the optical axis of light detected by the camera. The alignment light illuminates a substrate and mask, and reflected light is detected by the camera. A microlens array for exposure use is present between a mask alignment mark and a substrate alignment mark, whereby an erect unmagnified image reflected from the substrate alignment mark is formed on the mask. A control device then uses the mask alignment mark and the substrate alignment mark detected by the camera to perform alignment of the substrate and the mask. Alignment of the substrate and the mask can be performed with high accuracy thereby. | 06-19-2014 |
Patent application number | Description | Published |
20130222196 | WIRELESS DEVICE, AND INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE INCLUDING THE WIRELESS DEVICE - According to one embodiment, a wireless device includes a circuit board, a semiconductor chip, a sealing resin, a conductive film, and an antenna element. The semiconductor chip includes a transmitting/receiving circuit and is mounted on the circuit board. The sealing resin seals the semiconductor chip. The conductive film covers a first surface portion of the sealing resin. An aperture is formed in a portion of the conductive film that corresponds to a second surface portion of the sealing resin other than the first surface portion, and the second surface portion is included in a side surface of the sealing resin and closest to an antenna terminal connected to the antenna element. | 08-29-2013 |
20130222401 | SEMICONDUCTOR PACKAGE, AND INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE INCLUDING THE SEMICONDUCTOR PACKAGES - According to the embodiments, a semiconductor package includes a semiconductor chip, a first conductive layer, a second conductive layer, and a power feeder. The semiconductor chip is provided on a substrate, is sealed with a resin, and contains a transmission/reception circuit. The first conductive layer is grounded and covers a first region on a surface of the resin. The second conductive layer is not grounded and covers a second region on the surface of the resin other than the first region. A power feeder electrically connects the semiconductor chip to the second conductive layer. | 08-29-2013 |
20130225102 | WIRELESS DEVICE, AND INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE INCLUDING THE WIRELESS DEVICE - According to one embodiment, a wireless device includes a board, a semiconductor chip, a radiation element, a sealing resin, a conductive layer, and a first conductive wall. The semiconductor chip is mounted on the board and includes a transmission/reception circuit. The radiation element is formed on the board. The sealing resin seals the semiconductor chip. The conductive layer covers at least a portion of a surface of the sealing resin. The first conductive wall is provided between the semiconductor chip and the radiation element and is connected to the conductive layer. | 08-29-2013 |
20140015709 | WAVEGUIDE CONNECTING STRUCTURE, ANTENNA DEVICE AND RADAR DEVICE - There is provided a waveguide connecting structure, including first, second, third and fourth waveguides. A first coupling window at one of magnetic field planes of the third waveguide couples the first and third waveguides in such a manner that the electric field planes of both are in parallel. A second coupling window formed at one of the electric field planes of the third waveguide couples the second and third waveguides in such a manner that the electric field planes of the second waveguide is in parallel with the magnetic field planes of the first waveguide. A third coupling window formed at the other one of the electric field planes couples the fourth and third waveguides in such a manner that the electric field planes of the fourth waveguide is in parallel with the magnetic field planes of the first waveguide. | 01-16-2014 |
20140055939 | WIRELESS DEVICE, AND INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE INCLUDING THE WIRELESS DEVICE - According to one embodiment, a wireless device includes a circuit board, a semiconductor chip, a nonconductive layer, and a conductive film. The semiconductor chip includes a transmitting/receiving circuit and is mounted on the circuit board. The nonconductive layer is to seal the semiconductor chip. The conductive film is to cover a surface of the nonconductive layer, the conductive film being provided with a plurality of apertures serving as radiating elements. At least one aperture of the plurality of apertures is fed with power. | 02-27-2014 |
20140158774 | WIRELESS DEVICE - According to one embodiment, a wireless device is provided with a semiconductor chip, a substrate, an antenna, and a sealing material. The chip includes a wireless circuit. The substrate has a plurality of terminals arranged on a first surface and the chip arranged on a second surface. The antenna includes a radiation element and is electrically connected to the chip. The sealing material seals the chip and the antenna. A distance between a first wall of the sealing material substantially parallel to the second surface and the radiation element is equal to or more than a distance between a second wall of the sealing material substantially perpendicular to the second surface and the radiation element. | 06-12-2014 |
20140325150 | WIRELESS APPARATUS - According to one embodiment, a wireless apparatus includes a substrate, a first semiconductor chip, a transmission line, a non-conductive layer, a conductive layer and a wire. The first semiconductor chip is arranged on the substrate and includes a circuit which transmits and receives a signal. The transmission line includes a first portion which is formed in at least one of the substrate and the first semiconductor chip. The non-conductive layer seals the first semiconductor chip. The conductive layer covers a surface of the non-conductive layer, an opening being formed in at least a part of the conductive layer. The wire is connected to the first portion so as to extend from the first portion toward the opening and is arranged in a position in which the opening is excited. | 10-30-2014 |
Patent application number | Description | Published |
20090040263 | PRINTING POSITION ALIGNMENT METHOD AND PRINTING APPARATUS - Multiple alignment patterns, each composed of first and second alignment pattern elements printed by forward and backward movements of a print head, respectively, are formed while the relative printing positions of the two elements are shifted. From optical characteristics data thereof, whether the data is influenced by a disturbance is determined. When the data is determined to be less influenced by the disturbance and therefore to be reliable, an adjusting value for aligning positions in printing in reciprocal movements is calculated by use of: data with the smallest relative printing position misalignment between the first and second alignment pattern elements; and data of optical characteristics close to the data. When the data is largely influence by the disturbance, a range of shifting of relative position is widened than that of the data less influenced by the disturbance so that more data pieces are used to obtain the adjusting value. | 02-12-2009 |
20100277539 | PRINTING POSITION ALIGNMENT METHOD AND PRINTING APPARATUS - Multiple alignment patterns, each composed of first and second alignment pattern elements printed by forward and backward movements of a print head, respectively, are formed while the relative printing positions of the two elements are shifted. From optical characteristics data thereof, whether the data is influenced by a disturbance is determined. When the data is determined to be less influenced by the disturbance and therefore to be reliable, an adjusting value for aligning positions in printing in reciprocal movements is calculated by use of: data with the smallest relative printing position misalignment between the first and second alignment pattern elements; and data of optical characteristics close to the data. When the data is largely influence by the disturbance, a range of shifting of relative position is widened than that of the data less influenced by the disturbance so that more data pieces are used to obtain the adjusting value. | 11-04-2010 |
20120033007 | PRINTING POSITION ALIGNMENT METHOD AND PRINTING APPARATUS - Multiple alignment patterns, each composed of first and second alignment pattern elements printed by forward and backward movements of a print head, respectively, are formed while the relative printing positions of the two elements are shifted. From optical characteristics data thereof, whether the data is influenced by a disturbance is determined. When the data is determined to be less influenced by the disturbance and therefore to be reliable, an adjusting value for aligning positions in printing in reciprocal movements is calculated by use of: data with the smallest relative printing position misalignment between the first and second alignment pattern elements; and data of optical characteristics close to the data. When the data is largely influence by the disturbance, a range of shifting of relative position is widened than that of the data less influenced by the disturbance so that more data pieces are used to obtain the adjusting value. | 02-09-2012 |
Patent application number | Description | Published |
20090220894 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude. | 09-03-2009 |
20120328992 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes applying illumination light to a photomask, and projecting diffracted light components from the photomask via a projection optical system to form a photoresist pattern on a substrate. The photomask includes a plurality of opening patterns which are arranged on each of a plurality of parallel lines at regular second intervals in a second direction and which have regular first intervals in a first direction perpendicular to the second direction. The plurality of opening patterns arranged on the adjacent ones of the plurality of parallel lines are displaced from each other half the second interval in the second direction. Moreover, the dimensions of the plurality of opening patterns and the complex amplitude transmittance of nontransparent region in the photomask are set so that three of the diffracted light components passing through the pupil of the projection optical system have equal amplitude. | 12-27-2012 |
20150070681 | PATTERN GENERATING METHOD, PATTERN FORMING METHOD, AND PATTERN GENERATING PROGRAM - In general, according to one embodiment, a pattern generating method evaluates an amount of flare generated through a mask during an EUV exposure; calculates optimal coverage of a mask pattern for enhancing uniformity of the amount of flare in an exposure region by applying an optimization algorithm; and generates a dummy pattern of the mask based upon the coverage of the mask pattern. | 03-12-2015 |
Patent application number | Description | Published |
20090115784 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - Upon generation of an image of a virtual space on which a virtual object is laid out using a ray tracing method, an approximate virtual object, which is configured by at least one virtual element to approximate the shape of a physical object, is laid out on the virtual space. Then, intersect determination between a ray generated based on the ray tracing method and an object on the virtual space is executed. As a result of the intersect determination, when the ray and the approximate virtual object have a predetermined intersect state, a pixel corresponding to the ray is generated based on a ray before the predetermined intersect state is reached. | 05-07-2009 |
20090128552 | IMAGE PROCESSING APPARATUS FOR COMBINING REAL OBJECT AND VIRTUAL OBJECT AND PROCESSING METHOD THEREFOR - When an image in a virtual space in which a virtual object is arranged is generated using a ray tracing method, and when it is determined that a ray which is generated in accordance with the ray tracing method successively intersected an approximate virtual object such as a hand which is a real object at lest twice, an image corresponding to a first intersection is generated in accordance with the ray emitted to the first intersection. | 05-21-2009 |
20110148758 | COORDINATE INPUT APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - A coordinate input apparatus for making an input by bringing a pointing device into contact with an input area of an apparatus main body is provided, wherein the pointing device comprises: a timer configured to generate a transmission cycle by timekeeping; a detection unit configured to detect the presence/absence of an input instruction according to the presence/absence of contact of the pointing device with the input area; wherein when the detection unit detects the presence of the input instruction, and then detects the absence of the input instruction, the timer continues timekeeping of the transmission cycle during a predetermined holding period. | 06-23-2011 |
20130234955 | COORDINATE INPUT APPARATUS - A coordinate input apparatus includes a light projecting unit configured to project light parallelly to an effective coordinate input region, a reflection unit configured to retroreflect the light projected by the light projecting unit, and a light receiving unit configured to receive light from the light projecting unit or the reflection unit. The coordinate input apparatus includes a moving unit configured to move a set of the light projecting unit, light receiving unit, and reflection unit in a direction perpendicular to the effective coordinate input region in order to ensure a light amount with which a pointed position in the effective coordinate input region can be calculated based on variations of a light amount distribution obtained from the light receiving unit. | 09-12-2013 |
20130257814 | COORDINATE INPUT APPARATUS - A coordinate input apparatus includes a first housing and a second housing each of which incorporate at least two sensor units each including one of the light projecting unit and one of the light receiving unit. A pointed position to an effective coordinate input region is calculated based on variations of a light amount distribution obtained from the light receiving units of each of the first and second housings. In each of the first and second housings, the field range of a light receiving unit is almost parallel to the effective coordinate input region, the optical axis direction of the light receiving unit is a direction perpendicular to a line segment connecting the barycenters of at least two sensor units in a single housing, and the field range is set to be asymmetric to the optical axis direction. | 10-03-2013 |
Patent application number | Description | Published |
20090085774 | ONBOARD VEHICLE INFORMATION NOTIFYING APPARATUS, INFORMATION PROVIDING SYSTEM, AND INFORMATION NOTIFYING METHOD - An onboard vehicle information notifying apparatus is proved with a moving body position acquiring section, an information acquiring section, an information providing zone setting section and an information notifying section. The moving body position acquiring section acquires a moving body position for at least one moving body existing in a vicinity of a host vehicle. The information acquiring section acquires an advancement speed and an advancement direction of the host vehicle, and a prescribed movement speed of the moving body. The information providing zone setting section sets an information providing zone within which existence of the moving body should be reported, based on information acquired by the information acquiring section. The information notifying section reports the existence of the moving body when the position of the moving body acquired by the moving body position acquiring section exists within the information providing zone set by the information providing zone setting section. | 04-02-2009 |
20090088184 | MOVING BODY COMMUNICATION SYSTEM, MOVING BODY TERMINAL, INFORMATION PROVIDING APPARATUS, AND INFORMATION TRANSMISSION METHOD - A moving body terminal is basically provided with a position information acquiring section, a receiving section and a control section. The position information acquiring section is configured to acquire position information indicating a current position of the moving body terminal. The receiving section is configured to receive from an information providing apparatus simple map information which includes information transmission determining information indicating an information transmission unnecessary region of the simple map information where the position information of the moving body terminal is not required to be transmitted from the moving body terminal to the information providing apparatus. The control section is configured to prohibit a transmission of the position information to the information providing apparatus when the position information acquired by the position information acquiring section is inside the information transmission unnecessary region contained in the simple map information that was received. | 04-02-2009 |
20090088977 | CURRENT POSITION INFORMATION REPORTING SYSTEM, INFORMATION CENTER APPARATUS, AND METHOD THEREOF - An information center apparatus has a communication section, a motion information calculating section, a communication delay time calculating section, a communication cycle waiting time calculating section, an error estimating section and a correcting section. The communication section acquires reported current position information of a first moving body apparatus and reports a corrected current position information to a second moving body apparatus. The error estimating section estimate an error in the reported current position information with respect to an actual current position of the first moving body apparatus based on motion information calculated by the motion information calculating section, communication delay times calculated by the communication delay time calculating section, and a communication cycle waiting time calculated by the communication cycle waiting time calculating section. The correcting section corrects the reported current position information using the error estimated by the error estimating section to obtain the corrected current position information. | 04-02-2009 |
20120007728 | ONBOARD VEHICLE INFORMATION NOTIFYING APPARATUS - An onboard vehicle information notifying apparatus has a moving body position acquiring section that acquires a moving body position for at least one moving body existing in a vicinity of a host vehicle and that acquires map information of the vicinity of the host vehicle. The map information is divided into a plurality of unit regions, with each of the unit regions being a notification necessary region when the moving body exists in the unit region. An information acquiring section acquires an advancement speed and an advancement direction of the host vehicle, and a prescribed movement speed of the moving body. An information providing zone setting section sets an information providing zone within which existence of the moving body should be reported. The information notifying section reports the existence of the moving body when the information providing zone overlaps with the notification necessary region. | 01-12-2012 |
20120178475 | MOVING BODY TERMINAL, INFORMATION PROVIDING APPARATUS, AND INFORMATION TRANSMISSION METHOD - A moving body terminal is basically provided with a position information acquiring section, a receiving section and a control section. The position information acquiring section is configured to acquire position information indicating a current position of the moving body terminal. The receiving section is configured to receive from an information providing apparatus simple map information which includes information transmission determining information indicating an information transmission unnecessary region of the simple map information where the position information of the moving body terminal is not required to be transmitted from the moving body terminal to the information providing apparatus. The control section is configured to prohibit a transmission of the position information to the information providing apparatus when the position information acquired by the position information acquiring section is inside the information transmission unnecessary region contained in the simple map information that was received. | 07-12-2012 |
Patent application number | Description | Published |
20080204107 | MOS RESISTANCE CONTROLLING DEVICE AND MOS ATTENUATOR - A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors. | 08-28-2008 |
20080311867 | MOS RESISTANCE CONTROLLING DEVICE, MOS ATTENUATOR AND RADIO TRANSMITTER - A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors. | 12-18-2008 |
20090042521 | RADIO TRANSMITTER USING CARTESIAN LOOP - A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on. | 02-12-2009 |
Patent application number | Description | Published |
20090279356 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written. | 11-12-2009 |
20100124140 | POWER SUPPLY CIRCUIT AND NAND-TYPE FLASH MEMORY - A power supply circuit has a control circuit. The control circuit outputs a control clock signal so as to cause a first booster circuit to compulsorily perform boosting operation with a first boosting capability in response to an output signal of a second comparison amplifier after a lapse of a prescribed period since the first booster circuit is started to perform boosting operation with the first boosting capability in response to a first activation signal of a first comparison amplifier. | 05-20-2010 |
20100165735 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention comprises a voltage step-down circuit including a first and a second circuit to achieve a voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage, a transfer transistor to transfer the second voltage to a word line, and a control circuit to generate the second voltage as a first write voltage in a first mode wherein the first write voltage less than or equal to a prescribed magnitude is applied to the word line, and to generate the second voltage as a second write voltage in a second mode wherein the second write voltage greater than the prescribed magnitude is applied to the word line, wherein the difference between the first voltage and the second voltage is greater than or equal to the threshold voltage of the transfer transistor. | 07-01-2010 |
20100238722 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES AND VOLTAGE CONTROL CIRCUIT - A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2 | 09-23-2010 |
20110019477 | NAND TYPE FLASH MEMORY - According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block. | 01-27-2011 |
Patent application number | Description | Published |
20110164165 | FOCUS DETECTION APPARATUS, FOCUS DETECTION METHOD, AND IMAGE SENSING APPARATUS - A focus detection apparatus includes an image sensor that has a first pixel group which receives a luminous flux passing a first pupil area of an imaging optical system, and a second pixel group which receives a luminous flux passing a second pupil area different from the first pupil area; a storage unit that stores first and second distribution functions corresponding to the first and second pupil areas, respectively; a calculation unit that generates a first image signal by performing calculations on a first subject image, obtained from the first pixel group, using the second distribution function, and generates a second image signal by performing calculations on a second subject image, obtained from the second pixel group, using the first distribution function; and a focus state detection unit that detects a focus state of the imaging optical system based on the first and the second image signals. | 07-07-2011 |
20110169997 | SOLID-STATE IMAGE SENSING ELEMENT AND IMAGE SENSING APPARATUS - An image sensor that output a signal for detecting a focus state of a photographing lens. The image sensor includes a microlens; a light-receiving pixel; a first focus state detection pixel pair for outputting a focus state detection signal, in which aperture areas of the first focus state detection pixel pair are small in comparison to the light-receiving pixel; and a second focus state detection pixel pair for outputting a focus state detection signal, in which aperture areas of the second focus state detection pixel pair are small in comparison to the light-receiving pixel, wherein the second focus state detection pixel pair is arranged at a position that is shifted by a predetermined amount relative to each aperture position, with respect to the microlens of the first focus state detection pixel pair. | 07-14-2011 |
20120229696 | Image Capturing Apparatus - An image capturing apparatus comprises: an image sensor having image forming pixels for receiving light that has passed through an entire pupil area of an imaging lens which forms an object image, and focus detection pixels, which are arranged discretely among the image forming pixels, for receiving light that has passed through part of the pupil area of the imaging lens; a detection unit configured to detect an edge direction of an object based on an image signal acquired by the image sensor; an averaging unit configured to average image signals, while shifting a phase of the image signals, which are acquired respectively from each of the focus detection pixels, based on the edge direction detected by the detection unit; and a calculation unit configured to calculate a defocus amount of the imaging lens using the image signal averaged by the averaging unit. | 09-13-2012 |
20130188236 | LIGHT INTENSITY CONTROL APPARATUS - An arm member is capable of moving to a first position, a second position, a third position, and a fourth position, in order, by driving a stepping motor in one direction. A shutter blade is in a closed state and a light quantity adjustment blade is in an insertion state when the arm member is at the first position, the shutter blade is in an open state and the light quantity adjustment blade is in the insertion state when the arm member is at the second position, the shutter blade is in the open state and the light quantity adjustment blade is in the evacuation state when the arm member is at the third position, and the shutter blade is in the closed state and the light quantity adjustment blade is in the evacuation state when the arm member is at the fourth position. | 07-25-2013 |
20150054972 | IMAGING APPARATUS AND CONTROL METHOD AND PROGRAM OF IMAGING APPARATUS - An imaging apparatus having an image formation optical system having a lens for focus adjustment of an optical image of an object and an imaging unit for picking up the formed optical image and generating a pixel signal from which a refocus image can be generated includes: a calculation unit for obtaining information of the object the optical image of which is picked up by the imaging unit and calculating, based on the obtained object information, a range of a lens position at which the refocus image of the object being in-focus can be generated; a prediction unit for predicting, based on the lens position range, a change of the calculated lens position at which the refocus image of the object being in-focus can be generated; and a determination unit for determining a drive position of the lens based on a prediction result. | 02-26-2015 |