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| 20100110755 | FERROELECTRIC RANDOM ACCESS MEMORY DEVICE - A ferroelectric random access memory device has a first bit line, a first ferroelectric capacitor, a second bit line, a second ferroelectric capacitor and a first to fourth MOS transistor. The first bit line is changed to a first data potential according to first data stored in the first ferroelectric capacitor, the second bit line is changed to a second data potential according to second data obtained by inverting a logic of the first data, and then the second MOS transistor and the fourth MOS transistor are turned on. | 05-06-2010 |
| 20100124092 | FERROELECTRIC MEMORY DEVICE - According to an aspect of the present invention, there is provided a ferroelectric memory device including: a cell unit including: a first select transistor having a first source, a first drain, and a first gate, one of the first source and the first drain being connected to a bit line; and a memory cell unit having a plurality of first memory cells, each of the first memory cells including a first ferroelectric capacitor and a first memory transistor; and a ferroelectric memory fuse including: a second select transistor having a second source, a second drain, and a second gate connected to a second select line, one of the second source and the second drain being connected to one end of the bit line; and a memory fuse unit having a plurality of second memory cells, each of the second memory cells including a second ferroelectric capacitor and a second memory transistor. | 05-20-2010 |
| 20100157650 | FERROELECTRIC MEMORY - A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation. | 06-24-2010 |
| 20110058403 | FERRO-ELECTRIC RANDOM ACCESS MEMORY APPARATUS - A ferro-electric random access memory apparatus has a memory cell array in which a plurality of memory cells each formed of a ferro-electric capacitor and a transistor are arranged, word lines are disposed to select a memory cell, plate lines are disposed to apply a voltage to a first end of the ferro-electric capacitor in a memory cell, and bit lines are disposed to read cell data from a second end of the ferro-electric capacitor in the memory cell. The ferro-electric random access memory apparatus has a sense amplifier which senses and amplifies a signal read from the ferro-electric capacitor onto the bit line. The ferro-electric random access memory apparatus has a bit line potential control circuit which exercises control to pull down a voltage on an adjacent bit line adjacent to the selected bit line onto which the signal is read, before operation of the sense amplifier at time of data readout. | 03-10-2011 |
| 20110063886 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF THE SAME - A memory includes a cell region; a spare region including a spare block; a fuse region storing remedy information necessary for an access to the spare block instead of a remedy target block, the fuse region comprising non-defective cells in the remedy target block, or including cells in a first block of the spare region; an initial reading fuse storing a block address for identifying the remedy target block or the first block allocated as the fuse region, and a selection address for selecting a region in the remedy target block or a region in the first block allocated as the fuse region; and a controller configured to acquire the remedy information from the fuse region based on the block address and the selection address, and to change the access to the remedy target block to the access to the spare block based on the remedy information. | 03-17-2011 |
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| 20100020130 | LIQUID EJECTING HEAD, IMAGE FORMING APPARATUS, AND METHOD FOR MANUFACTURING LIQUID EJECTING HEAD - A liquid ejecting head includes multiple nozzles to eject liquid droplet, a vibration unit including a vibration plate, the vibration plate forming at least one wall face of multiple liquid paths that communicate with the respective nozzles, a driving member to move the vibration plate, and the vibration unit formed of laminated multi-layered member that includes a resin layer to form the vibration plate, a first metal layer located on one side of the resin layer, and a second metal layer located on the other side of the resin layer, and wherein the first and second metal layers are formed of different metals, that is, the first metal layer has an ionization tendency higher than that of hydrogen, the second metal layer has an ionization tendency lower than that of hydrogen. | 01-28-2010 |
| 20100053269 | LIQUID EJECTION HEAD, IMAGE FORMING APPARATUS EMPLOYING THE LIQUID EJECTION HEAD, AND METHOD OF MANUFACTURING THE LIQUID EJECTION HEAD - A liquid ejection head includes a nozzle formation member having a liquid repellent layer disposed on a droplet ejection face of a nozzle substrate in which one or more nozzle orifices is formed to eject droplets. The liquid repellent layer includes a first sub-layer and a second sub-layer. The first sub-layer contains a higher proportion of low-molecular-weight molecules than the second sub-layer. The second sub-layer contains a higher proportion of high-molecular-weight molecules than the first sub-layer. Both the first sub-layer and the second sub-layer are exposed on a surface of the nozzle formation member. | 03-04-2010 |
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| 20090040263 | PRINTING POSITION ALIGNMENT METHOD AND PRINTING APPARATUS - Multiple alignment patterns, each composed of first and second alignment pattern elements printed by forward and backward movements of a print head, respectively, are formed while the relative printing positions of the two elements are shifted. From optical characteristics data thereof, whether the data is influenced by a disturbance is determined. When the data is determined to be less influenced by the disturbance and therefore to be reliable, an adjusting value for aligning positions in printing in reciprocal movements is calculated by use of: data with the smallest relative printing position misalignment between the first and second alignment pattern elements; and data of optical characteristics close to the data. When the data is largely influence by the disturbance, a range of shifting of relative position is widened than that of the data less influenced by the disturbance so that more data pieces are used to obtain the adjusting value. | 02-12-2009 |
| 20100277539 | PRINTING POSITION ALIGNMENT METHOD AND PRINTING APPARATUS - Multiple alignment patterns, each composed of first and second alignment pattern elements printed by forward and backward movements of a print head, respectively, are formed while the relative printing positions of the two elements are shifted. From optical characteristics data thereof, whether the data is influenced by a disturbance is determined. When the data is determined to be less influenced by the disturbance and therefore to be reliable, an adjusting value for aligning positions in printing in reciprocal movements is calculated by use of: data with the smallest relative printing position misalignment between the first and second alignment pattern elements; and data of optical characteristics close to the data. When the data is largely influence by the disturbance, a range of shifting of relative position is widened than that of the data less influenced by the disturbance so that more data pieces are used to obtain the adjusting value. | 11-04-2010 |
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| 20090115784 | IMAGE PROCESSING APPARATUS AND IMAGE PROCESSING METHOD - Upon generation of an image of a virtual space on which a virtual object is laid out using a ray tracing method, an approximate virtual object, which is configured by at least one virtual element to approximate the shape of a physical object, is laid out on the virtual space. Then, intersect determination between a ray generated based on the ray tracing method and an object on the virtual space is executed. As a result of the intersect determination, when the ray and the approximate virtual object have a predetermined intersect state, a pixel corresponding to the ray is generated based on a ray before the predetermined intersect state is reached. | 05-07-2009 |
| 20090128552 | IMAGE PROCESSING APPARATUS FOR COMBINING REAL OBJECT AND VIRTUAL OBJECT AND PROCESSING METHOD THEREFOR - When an image in a virtual space in which a virtual object is arranged is generated using a ray tracing method, and when it is determined that a ray which is generated in accordance with the ray tracing method successively intersected an approximate virtual object such as a hand which is a real object at lest twice, an image corresponding to a first intersection is generated in accordance with the ray emitted to the first intersection. | 05-21-2009 |
| 20110148758 | COORDINATE INPUT APPARATUS, CONTROL METHOD, AND STORAGE MEDIUM - A coordinate input apparatus for making an input by bringing a pointing device into contact with an input area of an apparatus main body is provided, wherein the pointing device comprises: a timer configured to generate a transmission cycle by timekeeping; a detection unit configured to detect the presence/absence of an input instruction according to the presence/absence of contact of the pointing device with the input area; wherein when the detection unit detects the presence of the input instruction, and then detects the absence of the input instruction, the timer continues timekeeping of the transmission cycle during a predetermined holding period. | 06-23-2011 |
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| 20090085774 | ONBOARD VEHICLE INFORMATION NOTIFYING APPARATUS, INFORMATION PROVIDING SYSTEM, AND INFORMATION NOTIFYING METHOD - An onboard vehicle information notifying apparatus is proved with a moving body position acquiring section, an information acquiring section, an information providing zone setting section and an information notifying section. The moving body position acquiring section acquires a moving body position for at least one moving body existing in a vicinity of a host vehicle. The information acquiring section acquires an advancement speed and an advancement direction of the host vehicle, and a prescribed movement speed of the moving body. The information providing zone setting section sets an information providing zone within which existence of the moving body should be reported, based on information acquired by the information acquiring section. The information notifying section reports the existence of the moving body when the position of the moving body acquired by the moving body position acquiring section exists within the information providing zone set by the information providing zone setting section. | 04-02-2009 |
| 20090088184 | MOVING BODY COMMUNICATION SYSTEM, MOVING BODY TERMINAL, INFORMATION PROVIDING APPARATUS, AND INFORMATION TRANSMISSION METHOD - A moving body terminal is basically provided with a position information acquiring section, a receiving section and a control section. The position information acquiring section is configured to acquire position information indicating a current position of the moving body terminal. The receiving section is configured to receive from an information providing apparatus simple map information which includes information transmission determining information indicating an information transmission unnecessary region of the simple map information where the position information of the moving body terminal is not required to be transmitted from the moving body terminal to the information providing apparatus. The control section is configured to prohibit a transmission of the position information to the information providing apparatus when the position information acquired by the position information acquiring section is inside the information transmission unnecessary region contained in the simple map information that was received. | 04-02-2009 |
| 20090088977 | CURRENT POSITION INFORMATION REPORTING SYSTEM, INFORMATION CENTER APPARATUS, AND METHOD THEREOF - An information center apparatus has a communication section, a motion information calculating section, a communication delay time calculating section, a communication cycle waiting time calculating section, an error estimating section and a correcting section. The communication section acquires reported current position information of a first moving body apparatus and reports a corrected current position information to a second moving body apparatus. The error estimating section estimate an error in the reported current position information with respect to an actual current position of the first moving body apparatus based on motion information calculated by the motion information calculating section, communication delay times calculated by the communication delay time calculating section, and a communication cycle waiting time calculated by the communication cycle waiting time calculating section. The correcting section corrects the reported current position information using the error estimated by the error estimating section to obtain the corrected current position information. | 04-02-2009 |
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| 20080204107 | MOS RESISTANCE CONTROLLING DEVICE AND MOS ATTENUATOR - A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors. | 08-28-2008 |
| 20080311867 | MOS RESISTANCE CONTROLLING DEVICE, MOS ATTENUATOR AND RADIO TRANSMITTER - A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor being set to a second reference potential, and the drain of an I-th MOS transistor being connected to the source of an I+1-th MOS transistor, where I is an integer from 1 to N−1; a current source which is electrically disposed at connection node between the drain of the N-th MOS transistors and the second reference potential; and an operational amplifier having a first input terminal being supplied with a third reference potential, a second input terminal connected with the connection node and an output terminal being connected with gates of the MOS transistors. | 12-18-2008 |
| 20090042521 | RADIO TRANSMITTER USING CARTESIAN LOOP - A radio transmitter including a combiner which combines input I/Q signals with feedback I/Q signals, a power amplifier which amplifies the quadrature modulated signal, a detector which detects amplitude and phase differences between the input and feedback I/Q signals, a switch to turn on and off the feedback I/Q signals, a generator to generate control signals which minimizes the amplitude difference and the phase difference, in a state where a transmission power is set, during for a period during which the switch is turned off, an amplitude adjuster which adjusts an amplitude of the feedback RF signal, during a period during which the switch is turned on, and a phase adjuster which adjusts a phase of the local signal, during the period during which the switch is turned on. | 02-12-2009 |
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| 20090279356 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory includes first selective transistors connected between one end of cell strings and bit lines; second selective transistors connected between the other end of the cell strings and a cell source line; a dummy cell string; a first dummy selective transistor connected between one end of the dummy cell string and a dummy bit line and whose gate is connected to a first selective gate line; a second dummy selective transistor connected between the other end of the dummy cell string and the cell source line and whose gate is connected to a second selective gate line, wherein at a time of writing in a selected memory cell, a voltage of a first dummy bit line selected is driven to a different voltage from a voltage of an unselected bit line, and any of the dummy cell transistors connected to the first dummy bit line is written. | 11-12-2009 |
| 20100124140 | POWER SUPPLY CIRCUIT AND NAND-TYPE FLASH MEMORY - A power supply circuit has a control circuit. The control circuit outputs a control clock signal so as to cause a first booster circuit to compulsorily perform boosting operation with a first boosting capability in response to an output signal of a second comparison amplifier after a lapse of a prescribed period since the first booster circuit is started to perform boosting operation with the first boosting capability in response to a first activation signal of a first comparison amplifier. | 05-20-2010 |
| 20100165735 | NONVOLATILE SEMICONDUCTOR MEMORY - A nonvolatile semiconductor memory of an aspect of the present invention comprises a voltage step-down circuit including a first and a second circuit to achieve a voltage drop and configured to decrease the first voltage to a second voltage less than the first voltage, a transfer transistor to transfer the second voltage to a word line, and a control circuit to generate the second voltage as a first write voltage in a first mode wherein the first write voltage less than or equal to a prescribed magnitude is applied to the word line, and to generate the second voltage as a second write voltage in a second mode wherein the second write voltage greater than the prescribed magnitude is applied to the word line, wherein the difference between the first voltage and the second voltage is greater than or equal to the threshold voltage of the transfer transistor. | 07-01-2010 |
| 20100238722 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICES AND VOLTAGE CONTROL CIRCUIT - A memory includes a binary-code setter BCS and the thermometer-code setter TCS, the BCS includes resistance elements with resistance values of R×2 | 09-23-2010 |
| 20110019477 | NAND TYPE FLASH MEMORY - According to one embodiment, a NAND type flash memory includes a first transfer transistor disposed between first and second memory planes, the first potential transfer terminal of the first transfer transistor being commonly connected to a first word line in the first NAND block and a second word line in the third NAND block, a second transfer transistor disposed at a first end of the first memory plane, the first potential transfer terminal of the second transfer transistor being connected to a third word line in the second NAND block, and a third transfer transistor disposed at a second end of the second memory plane, the first potential transfer terminal of the third transfer transistor being connected to a fourth word line in the fourth NAND block. | 01-27-2011 |
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| 20110164165 | FOCUS DETECTION APPARATUS, FOCUS DETECTION METHOD, AND IMAGE SENSING APPARATUS - A focus detection apparatus includes an image sensor that has a first pixel group which receives a luminous flux passing a first pupil area of an imaging optical system, and a second pixel group which receives a luminous flux passing a second pupil area different from the first pupil area; a storage unit that stores first and second distribution functions corresponding to the first and second pupil areas, respectively; a calculation unit that generates a first image signal by performing calculations on a first subject image, obtained from the first pixel group, using the second distribution function, and generates a second image signal by performing calculations on a second subject image, obtained from the second pixel group, using the first distribution function; and a focus state detection unit that detects a focus state of the imaging optical system based on the first and the second image signals. | 07-07-2011 |
| 20110169997 | SOLID-STATE IMAGE SENSING ELEMENT AND IMAGE SENSING APPARATUS - An image sensor that output a signal for detecting a focus state of a photographing lens. The image sensor includes a microlens; a light-receiving pixel; a first focus state detection pixel pair for outputting a focus state detection signal, in which aperture areas of the first focus state detection pixel pair are small in comparison to the light-receiving pixel; and a second focus state detection pixel pair for outputting a focus state detection signal, in which aperture areas of the second focus state detection pixel pair are small in comparison to the light-receiving pixel, wherein the second focus state detection pixel pair is arranged at a position that is shifted by a predetermined amount relative to each aperture position, with respect to the microlens of the first focus state detection pixel pair. | 07-14-2011 |
