| Patent application number | Description | Published |
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| 20100306423 | INFORMATION PROCESSING SYSTEM AND DATA TRANSFER METHOD - An information processing system includes a master module for outputting a transfer state signal in correspondence to a data read instruction when the data read instruction is successively output plural times, the transfer state signal indicating that at least one data read instruction succeeds some one of the data read instructions; and a memory controller for, when receiving the some one of the data read instructions and the corresponding transfer state signal from the master module, supplying data corresponding to the some one of the data read instructions to the master module, while reading data corresponding to the at least one data read instruction, which succeeds the some one of the data read instructions, from a memory and holding the read data in accordance with the received transfer state signal. | 12-02-2010 |
| 20110161549 | MEMORY CONTROL DEVICE AND CACHE MEMORY CONTROLLING METHOD - A memory control device for controlling an access from a processing unit to a cache memory, the memory control device includes: an address estimation circuit for receiving a first read address of the cache memory from the processing unit and estimating a second read address on the basis of the first read address; an access start detection circuit for detecting an access start of accessing cache memory at the first read address and outputting an access start signal; a data control circuit for receiving read data from the cache memory and for outputting the read data to the processing unit; and a clock control circuit for controlling a read clock to be output to the processing unit in response to the access start signal, the processing unit receiving the read data from the data control circuit with the read clock. | 06-30-2011 |
| 20110314197 | DATA PROCESSING SYSTEM - Each of a plurality of master devices outputs a speed grade signal indicating a data transfer speed with a data transfer request. An arbiter arbitrates transfer requests and speed grade signals from the plurality of master devices. A clock enable generation circuit generates a clock enable signal with a varying ratio of a valid level according to the speed grade signal arbitrated by the arbiter. A slave device operates upon receiving a clock signal when the clock enable signal is at the valid level, and transfers data according to the transfer request arbitrated by the arbiter. Accordingly, the frequency of the clock signal which causes the slave device to operate may be changed for each transfer request, and a fine control of the power of the slave device may be easily performed. As a result, power consumption of the data processing system may be finely controlled. | 12-22-2011 |
| Patent application number | Description | Published |
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| 20080219445 | Communications audit support system - A communications audit support system is provided, which makes it possible to audit communications of an arbitrary encrypted communication session at any time. The communications audit support system of the present invention stores key information used for encrypted communication in a key management DB in association with a key ID each time the key information is created, stores IP addresses of a user terminal and a service providing server which perform an encrypted communication session using the key information in a communication state management DB in association with the key ID, and stores an encrypted packet sent in an encrypted communication session in a packet DB in association with IP addresses of a sender and a receiver of the encrypted packet. | 09-11-2008 |
| 20080301439 | Validation Server, Program and Verification Method - A technique of managing public keys updated by a certificate authority and a plurality of hash algorithms is provided. | 12-04-2008 |
| 20090300349 | VALIDATION SERVER, VALIDATION METHOD, AND PROGRAM - A validation server using HSM, which reduces required process time from receiving a validation request to responding with a validation result, and comprises a first software cryptographic module | 12-03-2009 |
| 20100122081 | METHOD OF VALIDATION PUBLIC KEY CERTIFICATE AND VALIDATION SERVER - In response to a validation request that includes second information identifying the certificate authority, key information of the certificate authority at issuance of the public key certificate, and information identifying the public key certificate, if the second information identifying the certificate authority included in the validation request corresponds to the first information identifying the certificate authority included in the authority certificate, and the information identifying the public key certificate included in the validation request does not exist in the revocation information, the validation server creates a validation result indicating that the public key certificate corresponding to the information identifying the public key certificate included in the validation request is valid. | 05-13-2010 |
| 20110004763 | CERTIFICATE VALIDATION METHOD AND CERTIFICATE VALIDATION SERVER AND STORAGE MEDIUM - A certificate validation method for causing a certificate validation server to receive a certificate validation request from a given terminal device, build a certification path of from a first certificate authority (CA) to a second CA, perform validation of the certification path, and send a validation result to the terminal which issued the certificate validation request is disclosed. The validation server detects either a key update of any given CA or a compromise of the given CA, acquires a certificate of relevant CA and first certificate status information and second certificate status information, stores the acquired information in a storage unit or, alternatively, updates the information stored in the storage based on the acquired information, and performs the building of a certification path and validation of the certification path by use of the information of the storage unit. | 01-06-2011 |
