Patent application number | Description | Published |
20080206847 | PROBE CONNECTOR ASSEMBLY AND METHOD OF USE - A probe assembly includes a tubular sleeve having a passage extending between a first end and an opposing second end. The tubular sleeve is movable between an extended position wherein the first end and the opposing second end are spaced apart and a collapsed position wherein the first end and the opposing second end are moved closer together. A connector is secured to the second end of the tubular sleeve, the connector having an opening extending therethrough that communicates with the passage of the tubular sleeve, a sealing layer removably covering the opening of the connector. An elongated probe has a first end and an opposing second end, the second end of the probe being positioned within the passage of the tubular sleeve, the second end of the probe being configured to pass through the opening of the connector when the sealing layer is removed therefrom. | 08-28-2008 |
20110117594 | PROBE CONNECTOR ASSEMBLY AND MEHTOD OF USE - A probe assembly includes a tubular sleeve having a passage extending between a first end and an opposing second end. The tubular sleeve is movable between an extended position wherein the first end and the opposing second end are spaced apart and a collapsed position wherein the first end and the opposing second end are moved closer together. A connector is secured to the second end of the tubular sleeve, the connector having an opening extending therethrough that communicates with the passage of the tubular sleeve, a sealing layer removably covering the opening of the connector. An elongated probe has a first end and an opposing second end, the second end of the probe being positioned within the passage of the tubular sleeve, the second end of the probe being configured to pass through the opening of the connector when the sealing layer is removed therefrom. | 05-19-2011 |
20120218855 | STIRRED TANK REACTOR SYSTEMS AND METHODS OF USE - A reactor system includes a flexible bag having an interior surface bounding a compartment. An elongated tubular connector is disposed within the compartment of the flexible bag, the tubular connector having a first end and an opposing second end, the first end of the tubular connector being coupled with the flexible bag. An impeller is disposed within the compartment of the flexible bag and is secured to the tubular connector. A drive shaft is removably received within the tubular connector such that rotation of the drive shaft facilitates rotation of the impeller. | 08-30-2012 |
20140106453 | STIRRED TANK REACTOR SYSTEMS AND METHODS OF USE - A method of mixing a fluid includes positioning a flexible bag into the chamber of a support housing, the support housing having a plurality of baffles positioned so that the bag folds around the baffles. A fluid is delivered into a compartment of the flexible bag. A mixing element, such as an impeller, is moved within the compartment of the flexible bag so as to mix the fluid therein. | 04-17-2014 |
Patent application number | Description | Published |
20090062134 | ASSAY IMAGING APPARATUS AND METHODS - A method of conducting an assay on a plurality of samples is provided. The method includes the steps of performing an assay at each sample site in a sample array having greater than 100 sample sites simultaneously illuminating each sample site using one or more LEDs, and simultaneously imaging each of the sample sites to produce imaging data pertinent to the optical effect of each site. Each assay provides an optical effect. | 03-05-2009 |
20110003699 | Thermal Cycler for Microfluidic Array Assays - A system for thermal cycling a plurality of samples. The system includes a case having a fluid-tight cavity defining an interior volume. A microfluidic array is disposed in the interior volume, the array including a sheet of material having a pair of opposed surfaces, a thickness, and a plurality of through-holes running through the thickness between the surfaces. A thermal cycler having at least one thermally controlled surface is adapted to thermally contact the case. | 01-06-2011 |
20120245038 | THERMAL CYCLING APPARATUS AND METHOD - A system for holding at least one of sample and reagent for analysis. The system includes a pair of parallel covers, at least one of which is light transmissive, of which pair a light transmissive cover forms a top, and of which pair the other forms a bottom. A frame is disposed between the covers to define, in relation to the covers, an interior volume. The frame and the covers are associated with one another to form a case, the case being substantially tight to liquids. A microfluidic array is disposed in the interior volume. The array includes a sheet of material having a pair of opposed surfaces, a thickness, and a plurality of through-holes running through the thickness between the surfaces, the through-holes containing at least one of sample and reagent. | 09-27-2012 |
20140179566 | Thermal Cycling Apparatus and Method - A system for holding at least one of sample and reagent for analysis. The system includes a pair of parallel covers, at least one of which is light transmissive, of which pair a light transmissive cover forms a top, and of which pair the other forms a bottom. A frame is disposed between the covers to define, in relation to the covers, an interior volume. The frame and the covers are associated with one another to form a case, the case being substantially tight to liquids. A microfluidic array is disposed in the interior volume. The array includes a sheet of material having a pair of opposed surfaces, a thickness, and a plurality of through-holes running through the thickness between the surfaces, the through-holes containing at least one of sample and reagent. | 06-26-2014 |
20140332112 | Microfluidic Transfer Pins - A liquid dispenser for a microfluidic assay system is described. The dispenser includes at least one transfer pin for transferring a microfluidic sample of liquid to a target receptacle. A pin tip at one end of the transfer pin is structured to cooperate with an opening in the target receptacle. The tip uses a high voltage potential to transfer the sample from the pin to the receptacle. | 11-13-2014 |
Patent application number | Description | Published |
20090147692 | COLLECTING NETWORK PERFORMANCE DATA FROM MULTIPLE AUTONOMOUS SYSTEMS - A computer apparatus comprises first Border Gateway Protocol (BGP) logic comprising BGP route table data; a network interface to communicatively couple to a first autonomous system; data collection logic in computer-readable storage media when executed operable to perform discovering an address prefix of a data collector that is communicatively coupled to second BGP logic of a router within a second autonomous system that is coupled to the first autonomous system, wherein the second autonomous system is independent of the first autonomous system; determining a path through the first autonomous system, the one or more networks or intemetworks, and the second autonomous system to the data collector based on the BGP route table; requesting the data collector to provide one or more data values relating to performance of network elements of the second autonomous system; receiving and storing the one or more data values. | 06-11-2009 |
20120300780 | COLLECTING NETWORK PERFORMANCE DATA FROM MULTIPLE AUTONOMOUS SYSTEMS - A computer apparatus comprises first Border Gateway Protocol (BGP) logic comprising BGP route table data; a network interface to communicatively couple to a first autonomous system; data collection logic in computer-readable storage media when executed operable to perform discovering an address prefix of a data collector that is communicatively coupled to second BGP logic of a router within a second autonomous system that is coupled to the first autonomous system, wherein the second autonomous system is independent of the first autonomous system; determining a path through the first autonomous system, the one or more networks or internetworks, and the second autonomous system to the data collector based on the BGP route table; requesting the data collector to provide one or more data values relating to performance of network elements of the second autonomous system; receiving and storing the one or more data values. | 11-29-2012 |
20130036213 | VIRTUAL PRIVATE CLOUDS - Techniques are described for providing a virtual private cloud in a multi-tenant environment. Embodiments receive a request specifying cloud-based computing resources hosted by one or more cloud providers to integrate into a virtual private cloud with enterprise computing resources, the resources within the virtual private cloud are communicatively coupled at a common logical network level. Embodiments provision a cloud network device to integrate the cloud-based computing resources into the virtual private cloud. Additionally, the enterprise network device is configured to associate the enterprise computing resources with the virtual private cloud. Network packets between applications running on the enterprise computing resources and applications running on the cloud-based computing resources are then forwarded over the common logical network. | 02-07-2013 |
20130041728 | REAL TIME SERVICE ADVERTISEMENT FOR BILLING AND REVENUE SETTLEMENT IN A FEDERATED MODEL - Techniques are described for fulfilling a request for services in a federated peering environment. Embodiments receive an advertisement of offered services from each of a plurality of service providers. Such an advertisement may specify a list of offered services and pricing information for the services. A request for one or more services is received from a client at a first service provider. Embodiments determine a second service provider from the plurality of service providers to peer with to dynamically create a federation of peers for fulfilling the service request, based on the received advertisements of offered services and the requested services. Embodiments then peer with at least the determined second service provider to dynamically create a peered federation and fulfill the service request through the created federation of peers. | 02-14-2013 |
Patent application number | Description | Published |
20090132736 | MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS - A memory buffering system is disclosed that arbitrates bus ownership through all arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures. | 05-21-2009 |
20100281293 | REPLACING RESET PIN IN BUSES WHILE GUARANTEEING SYSTEM RECOVERY - Systems and methods are disclosed that replace a separate reset pin in a bus with a reset command that guarantees a system recovery. The system comprises a host component circuitry residing on a first chip and a client component circuitry residing on a second, different chip. A bus connects the host component circuitry to the client component circuitry. The host component circuitry is configured to transfer an initial client value associated with a client component time period to the client component circuitry over the bus on a periodic time basis. The periodic time basis is dictated by a host component time period and the client component time period is greater than the host component time period. The client component circuitry is configured to initiate a reset procedure if the client component time period expires which indicates that the initial client value was not received at a next time on the periodic time basis dictated by the host component time period. | 11-04-2010 |
20110082694 | REAL-TIME DATA PATTERN ANALYSIS SYSTEM AND METHOD OF OPERATION THEREOF - A method for real-time data-pattern analysis. The method includes receiving and queuing at least one data-pattern analysis request by a data-pattern analysis unit controller. At least one data stream portion is also received and stored by the data-pattern analysis unit controller, each data stream portion corresponding to a received data-pattern analysis request. Next, a received data-pattern analysis request is selected by the data-pattern analysis unit controller along with a corresponding data stream portion. A data-pattern analysis is performed based on the selected data-pattern analysis request and the corresponding data stream portion, wherein the data-pattern analysis is performed by one of a plurality of data-pattern analysis units. | 04-07-2011 |
20120063243 | APPARATUS AND METHOD FOR DATA CAPTURE USING A READ PREAMBLE - A data capturing device is provided. The data capturing device includes a data capturing device controller and data capturing components. The data capturing device is arranged to send a burst read command. Each of the data capturing components includes a DLL component, a data sampling component, a comparison component, and a valid clock calculation component. The DLL component is arranged to provide clock signals. The data sampling component is arranged to receive a serial data signal that includes a read preamble, where the read preamble includes a training pattern, and to sample the serial data signal with each of the clock signals. The comparison component is arranged to compare each of the sampled data signals with an expected training pattern. The valid clock calculation component is arranged to, based on the comparisons, select one of the clock signals as the valid clock signal for locking the DLL component to. | 03-15-2012 |
20140040587 | Power Savings Apparatus and Method for Memory Device Using Delay Locked Loop - Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle. | 02-06-2014 |
20140223054 | MEMORY BUFFERING SYSTEM THAT IMPROVES READ/WRITE PERFORMANCE AND PROVIDES LOW LATENCY FOR MOBILE SYSTEMS - A memory buffering system is disclosed that arbitrates bus ownership through an arbitration scheme for memory elements in chain architecture. A unified host memory controller arbitrates bus ownership for transfer to a unified memory buffer and other buffers within the chain architecture. The system is used within a communication system with a bus in chain architectures and parallel architectures. | 08-07-2014 |
20140365744 | Programmable Latency Count to Achieve Higher Memory Bandwidth - Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device. | 12-11-2014 |
20150106664 | METHOD FOR PROVIDING READ DATA FLOW CONTROL OR ERROR REPORTING USING A READ DATA STROBE - Disclosed herein are system, apparatus, methods and/or combinations and sub-combinations thereof, for using a read data strobe signal received at a host device from a peripheral device to convey variable latency (flow) control or report an error in the data content read from the peripheral device. Reception of the read data strobe signal before a predetermined maximum latency time, provides variable latency control back to the host by indicating when valid data is available for capture. If the read data strobe signal is not received before expiration of a predetermined maximum latency time, the peripheral controller is indicating a read data error back to the host. | 04-16-2015 |
20150242129 | MEMORY SUBSYSTEM WITH WRAPPED-TO-CONTINUOUS READ - Disclosed herein are system, method, and computer program product embodiments for accessing data of a memory. A method embodiment operates by receiving one or more requests for data stored across at least a first memory area and a second memory area of a memory. The method continues with performing, by at least one processor, a wrapped read of data within a first memory area of the memory. The method then performs, by the at least one processor, a continuous read of data within a second memory area of the memory, the second memory area being adjacent to the first memory area. The continuous read starts at a first boundary of the second memory area, and is performed automatically after the wrapped read of data within the first memory area. | 08-27-2015 |
20150378882 | BOOTING AN APPLICATION FROM MULTIPLE MEMORIES - Disclosed herein are system, apparatus, article of manufacture, method and/or computer program product embodiments for booting an application from multiple memories. An embodiment operates by executing in place from a first memory a first portion of the application, loading a second portion of the application from a second memory, and executing the second portion of the application. | 12-31-2015 |
20160103723 | SYSTEM-ON-CHIP VERIFICATION - Disclosed herein are method, system and computer program product embodiments for improving the verification process of a system on chip (SoC). An embodiment operates by employing an active interconnect (AIC) between a processing subsystem (e.g., a central processing unit or CPU) and a plurality of peripherals, wherein the processing subsystem is linked to a plurality of applications via a plurality of drivers, and implementing a common set of software codes by at least one of the applications for a software development process and a hardware verification process. The AIC includes a plurality of communication protocols. During the software development process, the AIC configures at least one of the communication protocols to not enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a high-level programming language model is used for the peripherals. During the hardware verification process, the AIC configures at least one of the communication protocols to enforce a timing limitation on one or more transactions between the processing subsystem and at least one of the peripherals, and a register-transfer level model is used for a least one of the plurality of peripherals. The AIC may further configure at least one of the communication protocols to enforce one or more constraints on the transactions to achieve increased hardware verification coverage. | 04-14-2016 |