| Patent application number | Description | Published |
|---|
| 20080198654 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: first and second cell arrays each having a plurality of memory cells; and a sense amplifier circuit for reading out data of the first and second cell arrays, wherein plural information cells and at least one reference cell are set in each of the first and second cell arrays, one of four data levels L | 08-21-2008 |
| 20080258129 | Phase-Change Memory Device - A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR. | 10-23-2008 |
| 20080310211 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a semiconductor substrate; at least one cell array formed above the semiconductor substrate, each memory cell having a stack structure of a variable resistance element and an access element, the access element having such an off-state resistance value in a certain voltage range that is ten times or more as high as that in a select state; and a read/write circuit formed on the semiconductor substrate as underlying the cell array, wherein the variable resistance element comprises a recording layer formed of a first composite compound expressed by A | 12-18-2008 |
| 20090003047 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair and coupled to differential input nodes in the sense amplifier array. | 01-01-2009 |
| 20090049366 | MEMORY DEVICE WITH ERROR CORRECTION SYSTEM - There is disclosed a memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: divide an error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of the solution candidates with those of the syndromes, the corresponding relationships being previously obtained as a table, thereby obtaining error locations. | 02-19-2009 |
| 20090109729 | RESISTANCE CHANGE MEMORY DEVICE AND METHOD FOR ERASING THE SAME - A resistance change memory device including a cell array with memory cells arranged therein to store a resistance value as data in a non-volatile manner, and an erase circuit configured to set the memory cells in the cell array in a reset state prior to data writing, wherein the erase circuit includes: an erase current generating circuit configured to output erase current of the cell array; multiple switch devices so disposed on current paths between the erase current generating circuit and the respective divided areas defined in the cell array as to supply the erase current to the divided areas; and a control circuit configured to sequentially turn on the switch devices. | 04-30-2009 |
| 20090122598 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell. | 05-14-2009 |
| 20090198881 | MEMORY SYSTEM - A memory system including: a memory device; an ECC system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors; an address generating circuit for generating internal addresses in place of bad area addresses in accordance with the waning signal, the progressing of the internal addresses being selected as to avoid address collision with the address progressing of the memory device at least at the beginning; and a CAM for storing the internal addresses as substitutive area addresses, the CAM being referred to at an access time of the memory device so as to generate the substitutive area addresses in place of the bad area addresses in accordance with the warning signal. | 08-06-2009 |
| 20090213639 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a memory cell array with first wirings, second wirings, and memory cells, the memory cell including a diode and a variable resistance element, anode of diodes being located on the first wiring side, wherein the memory cell array is sequentially set in the following three states after power-on: a waiting state defined by that both the first and second wirings are set at a first voltage; a standby state defined by that the first wirings are kept at the first voltage and the second wirings are set at a second voltage higher than the first voltage; and an access state defined by that a selected first wiring and a selected second wiring are set at a third voltage higher than the first voltage and the first voltage, respectively. | 08-27-2009 |
| 20090261315 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the circuit, wherein the vertical wirings include multi-layered metal pieces, each layer of which has a plurality of the metal pieces dispersedly arranged in a stripe-shaped contact trench formed on an interlayer insulating film in the elongated direction. | 10-22-2009 |
| 20090279344 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively. | 11-12-2009 |
| 20100008126 | THREE-DIMENSIONAL MEMORY DEVICE - A three-dimensional memory device includes: a plurality of mats laminated therein, each having memory cells arranged in a two-dimensional manner; and access signal lines and data lines to select memory cells in each mat being shared between respective adjacent mats. Laminated mats are divided into three or more groups. When selecting one of these groups, memory cells in some of the remaining groups are biased so that a leakage current flows therethrough, while memory cells in the rest of the remaining groups are biased so that a leakage current does not flow therethrough. | 01-14-2010 |
| 20100054019 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line. | 03-04-2010 |
| 20100115383 | MEMORY DEVICE WITH AN ECC SYSTEM - A memory device has an error detection and correction system constructed on a Galois finite field. The error detection and correction system includes calculation circuits for calculating the finite field elements based on syndromes obtained from read data and searching error locations, the calculation circuits having common circuits, which are used in a time-sharing mode under the control of internal clocks. | 05-06-2010 |
| 20100162068 | MEMORY DEVICE - A memory device including: a memory cell array; an error-detecting and correcting circuit; and a buffer register disposed for temporally storing write and read data. Write data loaded in the buffer register are encoded in the error-detecting and correcting circuit to be over-written in the buffer register together with check bits, and then transferred to be written into the cell array. Read data read from the cell array and held in the buffer register together with check bits are decoded in the error-detecting and correcting circuit to be corrected, over-written in the buffer register and then output. | 06-24-2010 |
| 20100165702 | THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY - A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array. | 07-01-2010 |
| 20100235714 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the difference of the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array. | 09-16-2010 |
| 20100259970 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including a substrate, first and second wiring lines formed above the substrate to be insulated from each other, and memory cells disposed between the first and second wiring lines, wherein the memory cell includes: a variable resistance element for storing as information a resistance value; and a Schottky diode connected in series to the variable resistance element. The variable resistance element has: a recording layer formed of a composite compound containing at least one transition element and a cavity site for housing a cation ion; and electrodes formed on the opposite sides of the recording layer, one of which serves as a cation source in a write or erase mode for supplying a cation to the recording layer to be housed in the cavity site therein. | 10-14-2010 |
| 20100259975 | PHASE CHANGE MONEY DEVICE - A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit. | 10-14-2010 |
| 20110019462 | THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY - A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array. | 01-27-2011 |
| 20110051492 | RESISTANCE CHANGE MEMORY DEVICE - A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode. | 03-03-2011 |
