Patent application number | Description | Published |
20090298254 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In a semiconductor device manufacturing method, a surface of a substrate structure including a semiconductor layer is covered with a first film including first and second openings. The first opening is configured as an alignment mark. The second opening is configured as an opening for introducing an impurity into a first predetermined position of the semiconductor layer. In this method, a third opening is formed in the first film, using a photo mask aligned with the first opening used as an alignment mark. The third opening is configured as an opening for introducing an impurity into a second predetermined position of the semiconductor layer. | 12-03-2009 |
20100052182 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING THE SAME - A lack of exposure margin is avoided in a region, where an interconnection is required in a direction different from that of an interconnection of a region where an exposure condition is optimized. A semiconductor device According to an aspect of the invention includes a semiconductor substrate | 03-04-2010 |
20100084703 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more. | 04-08-2010 |
20100270606 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME - A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm. | 10-28-2010 |
20110193155 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A STACKED GATE HAVING A CHARGE STORAGE LAYER AND A CONTROL GATE, AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device includes a source region, a drain region, a channel region, a charge storage layer, and a control gate electrode. The source region and drain region are formed separately from each other in a surface of a semiconductor substrate. The channel region is formed in the semiconductor substrate and located between the source region and the drain region. The charge storage layer is formed on the channel region with a first insulating film interposed therebetween. The control gate electrode is formed on the charge storage layer with a second insulating film interposed therebetween. The control gate has an upper corner portion rounded with a radius of curvature of 5 nm or more. | 08-11-2011 |
20120037974 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a semiconductor device includes a resistor element and a stacked-gate type memory cell transistor. The resistor element includes a first conductive layer which is formed on a second conductive layer via a first insulating layer, and is electrically connected to an interconnect, the second conductive layer being on a substrate and in a floating state. The stacked-gate type memory cell transistor is on the substrate, and includes a floating gate formed of the same material as the second conductive layer. | 02-16-2012 |
Patent application number | Description | Published |
20090058573 | Power switching apparatus and method of controlling the same - A power switching apparatus includes a breaker unit, an operating unit, a measuring unit, and a controlling unit. The breaker unit is connected on a three-phase current line, and includes switches each corresponding to one of phases of the three-phase current line. The operating unit simultaneously turns on or off the switches. The measuring unit measures a current flowing in each phase, and determines a time point where current flowing in one of the phases becomes zero as a reference time point. The controlling unit controls, when interrupting load current, the operating unit to turn off the switches in a range from 20 degrees to 40 degrees of an electric angle from the reference time point. | 03-05-2009 |
20100072828 | PHASE CONTROL SWITCHING DEVICE - In a phase control switching device that controls a closing phase of a three-phase switching device connected between a power-supply-side transmission line and a compensation transmission line having a shunt reactor, a closing-phase control unit operates based on a closing command to the three-phase switching device, generates, for each phase, a closing phase in which the three-phase switching device is closed at zero points, both polarities of which are inverted into the same polarity, among zero points where zero points of a voltage changing ratio and zero points of the shunt reactor current coincide with each other, and controls the three-phase switching device. | 03-25-2010 |
20100085668 | PHASE-CONTROL SWITCHING APPARATUS AND SWITCHING CONTROL METHOD FOR PHASE-CONTROL SWITCHING APPARATUS - A residual-magnetic-flux calculating unit includes a voltage-change-rate detecting unit that detects a transformer-voltage change rate from a phase voltage between a breaker and a transformer, a residual-magnetic-flux detecting unit that detects a residual magnetic flux remaining on the transformer based on the phase voltage, and a breaker-switching-state identifying unit that detects a switching state of the breaker. The residual-magnetic-flux calculating unit recalculates the residual magnetic flux based on the transformer-voltage change rate and a predetermined threshold while the breaker is in an open state. | 04-08-2010 |
20120293896 | INRUSH-CURRENT SUPPRESSING DEVICE AND INRUSH-CURRENT SUPPRESSING METHOD - An inrush-current suppressing device includes a residual-magnetic-flux calculation unit that obtains a residual magnetic flux generated within a three-phase transformer, an input magnetic-flux-error calculation unit that obtains a closing-phase input magnetic-flux error, a closing-order determination unit that determines a closing order of phases of a three-phase breaker, a target-closing-phase/time setting unit that sets a time from a reference point to a target closing phase of a first closing phase as a first target closing time, and sets a time obtained by adding up a time from the reference point to a target closing phase of a second closing phase and a delay time set to exclude a period in which a magnetic flux in the first closing phase possibly saturates as a second target closing time, and a closing control unit that generates and outputs a closing control signal to close each phase at the target closing time. | 11-22-2012 |