| Patent application number | Description | Published |
|---|
| 20080203575 | Integrated Circuit with Re-Route Layer and Stacked Die Assembly - An apparatus and a method of manufacture for a stacked-die assembly. A first die is placed on a substrate such that the backside of the die, i.e., the side opposite the side with the bond pads, is coupled to the substrate, preferably by an adhesive. Wire leads electrically couple the bond pads of the first die to contacts on the substrate. A second die is placed on the first die, and wire leads electrically couple the bond pads of the second die to contacts on the substrate. Preferably, a spacer is placed between the first die and the second die. Additional dies may be stacked on the second die. | 08-28-2008 |
| 20090045512 | CARRIER SUBSTRATE AND INTEGRATED CIRCUIT - A carrier substrate comprising a through contact connecting a first contact field on a top face of the carrier substrate to a second contact field on a bottom face of the carrier substrate and a substrate material being provided around the through contact. | 02-19-2009 |
| 20090072398 | INTEGRATED CIRCUIT, CIRCUIT SYSTEM, AND METHOD OF MANUFACTURING - An integrated circuit, a circuit system and method of manufacturing such is disclosed. One embodiment provides a circuit chip including a first contact field on a chip surface; and an insulating layer on the chip surface. The insulating layer includes a flexible material. A contact pillar is coupled to the first contact field and extends from the chip surface through the insulating layer. The contact pillar includes a conductive material. | 03-19-2009 |
| 20090102035 | Semiconductor Packaging Device - Embodiments of the invention relate to a semiconductor module and to a method for manufacturing a semiconductor module. In an embodiment of the invention, a semiconductor module for mounting to a board may include at least an integrated circuit having connections on at least one side of the integrated circuit, and at least a first layer which is applied to the side of the integrated circuit having the connections, wherein the free surface of the first layer facing away from the integrated circuit has a thermo-mechanical linear expansion in the in-plane direction of the surface which corresponds to the thermo-mechanical linear expansion of the board to which the semiconductor module is to be mounted. | 04-23-2009 |
| 20090194881 | Method for Manufacturing a Wafer Level Package - A method for manufacturing a wafer level package of an integrated circuit element for direct attachment to a wiring board is disclosed. An integrated circuit element includes input/output pads located on an active side. A non-conductive support structure is formed on the active side of the integrated circuit element in an area that is free from input/output pads. A conductive path is formed upon the support structure and a non-conductive coating is formed on over the active side of the integrated circuit element such that a surface is formed which leaves interface pads accessible. | 08-06-2009 |
| 20090212420 | INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING SAME - Fabricating an integrated circuit device includes providing a semiconductor substrate comprising a first surface and a sec-ond surface, forming a wiring layer on the first surface of the semiconductor substrate, providing a circuit chip, and arranging the circuit chip on the wiring layer of the semi-conductor substrate. The fabricating further includes forming an embedding layer on the wiring layer and on the circuit chip, the embedding layer encapsulating the circuit chip, thinning the semiconductor substrate at the second surface after forming the embedding layer, and forming a conductive via in the semiconductor substrate being electrically coupled to the wiring layer and exposed at the second surface of the semiconductor substrate. Moreover, an integrated circuit de-vice is described. | 08-27-2009 |
| 20090212438 | INTEGRATED CIRCUIT DEVICE COMPRISING CONDUCTIVE VIAS AND METHOD OF MAKING THE SAME - A semiconductor substrate for an integrated circuit device comprises at least one insulating substrate region being formed of a cohesive insulating material. The insulating substrate region includes at least two conductive vias extending at least between a first surface and a second surface of the insulating substrate region. | 08-27-2009 |
| 20090218690 | Reduced-Stress Through-Chip Feature and Method of Making the Same - A feature is inscribed in a major surface of a microelectronic workpiece having a material property expressed as a reference coefficient value. The feature includes a first material having a first coefficient value for the material property and a second material having a second coefficient value for the material property. The first coefficient value is different from the reference coefficient value different from the first coefficient value and the second coefficient value is different from the first coefficient value. The first and second materials behave as an aggregate having an aggregate coefficient value for the material property between the first coefficient value and the reference coefficient value. | 09-03-2009 |
| 20090243047 | Semiconductor Device With an Interconnect Element and Method for Manufacture - A semiconductor device is provided configured to be electrically connected to another device by through silicon interconnect technology. The semiconductor device includes a semiconductor substrate with at least one through hole. A through silicon conductor extends inside the through hole from the upper side to the bottom side of the semiconductor substrate. The through silicon conductor is electrical isolated from the semiconductor substrate and includes a conductor bump at one of its ends. Between the inner surface of the through hole and the through silicon conductor a gap is formed. The gap surrounds the through silicon conductor on one side of the semiconductor substrate having the conductor bump, and extends from this side of the substrate into the substrate. The gap is filled with a flexible dielectric material. | 10-01-2009 |
| 20090256258 | SEMICONDUCTOR CHIP WITH INTEGRATED VIA - An integrated circuit with a substrate with a lower and an upper surface is described. A via extends between the upper and the lower surface of the substrate. The via contains a conductive filling material that comprises carbon. | 10-15-2009 |
| 20090273097 | Semiconductor Component with Contact Pad - A structure and method of forming low cost bond pads is described. In one embodiment, the invention includes depositing an insulating layer over a last metal line of a substrate and forming an opening in the insulating layer. A colloid is printed over the insulating layer and fills the opening in the insulating layer. A conductive via and bond pads are formed by heating the colloid. | 11-05-2009 |
| 20090321959 | Chip Arrangement and Method of Manufacturing a Chip Arrangement - A chip arrangement includes a logic chip with electric contacts arranged on one side, at least one memory chip arrangement with electrical contacts arranged on at least one side, and a substrate with electrical contacts on both sides of the substrate. The logic chip is attached to the substrate and is electrically conductively coupled to the substrate. The memory chip arrangement is arranged on the logic chip on the side facing the substrate and is electrically conductive coupled to the logic chip. The substrate includes a plurality of electrical connections between the contacts of the one and the other side. | 12-31-2009 |
| 20100013101 | Method for Manufacturing a Multichip Module Assembly - A multichip module assembly includes a chipset of at least two chips. The chips have active sides, rear sides and chip contacts on their active sides adjacent each other and are embedded in a polymer matrix in a symmetrical manner relating to the top and the bottom surface of the chipset. Chip contacts are electrically connected by through polymer connectors that each extend from a chip contact to a surface of the polymer matrix. A film wiring line is arranged on a side of the polymer matrix for electrical connection of two through polymer connectors of two chips or a through polymer connector with an interconnect element arranged on a side of the polymer matrix. | 01-21-2010 |
| 20100065949 | Stacked Semiconductor Chips with Through Substrate Vias - Structures and methods of forming stacked chips are disclosed. In one embodiment, a first chip is disposed over a second chip, a top surface of the first and the second chip includes active circuitry. A first through substrate via is disposed within the first chip, the first through substrate via includes a protruding tip projecting below a bottom surface of the first chip, the bottom surface being opposite the top surface. A second through substrate via is disposed on the second chip, the second through substrate via including an opening, wherein the first protruding tip of the first chip is disposed within the opening of the second chip. | 03-18-2010 |
| 20100072579 | Through Substrate Conductors - Structures and methods of forming through substrate vias are disclosed. In one embodiment, the method includes forming a through substrate opening from a top surface of a substrate, the top surface including active devices, and filling the first through substrate opening with an ancillary material. A conductive capping layer is formed over the ancillary material to cap the first through substrate opening. The substrate is thinned from a back surface to expose a portion of the ancillary material, the back surface being opposite to the top surface. The ancillary material is removed from the first through substrate opening, and a conductor is formed by filling a conductive material into the through substrate opening. | 03-25-2010 |
| 20100090322 | Packaging Systems and Methods - Packaging systems and methods for semiconductor devices are disclosed. In one embodiment, a packaging system includes a first plate having a first coefficient of thermal expansion (CTE). An integrated circuit is mountable to the first plate. The packaging system includes a second plate coupleable over the first plate over the integrated circuit. The second plate has a second CTE that is substantially a same CTE as the first CTE. A plurality of solder balls is coupleable to the first plate or the second plate and to the integrated circuit. | 04-15-2010 |
| 20110068485 | COMPONENT AND METHOD FOR PRODUCING A COMPONENT - A component and a method for producing a component are disclosed. The component comprises an integrated circuit, a housing body, a wiring device overlapping the integrated circuit and the housing body, and one or more external contact devices in communication with the wiring device. | 03-24-2011 |
