Patent application number | Description | Published |
20080215822 | PCI Express Enhancements and Extensions - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-04-2008 |
20090069910 | ENCAPSULATION OF HIGH DEFINITION AUDIO DATA OVER AN INPUT/OUTPUT INTERCONNECT - Embodiments of the invention are generally directed to systems, methods, and apparatuses for encapsulation of high definition audio data over an input/output interconnect. In some embodiments, a system includes tunneling logic coupled with a high definition (HD) audio controller. The tunneling logic may receive digital audio data from the HD audio controller, encapsulate the digital audio data in a message suitable for an in-band input/output (IO) interconnect, and send the message to an add-in graphics card via the in-band input/output IO interconnect. Other embodiments are described and claimed. | 03-12-2009 |
20090193164 | General Input/Output Architecture, Protocol and Related Methods to Implement Flow Control - An enhanced general input/output communication architecture, protocol and related methods are presented. In one embodiment, a method for an enhanced general input/output communication architecture includes initializing a flow control mechanism within an general input/output (GIO) interface associated with a virtual channel upon initialization of the virtual channel, and tracking receive buffer availability in a remote GIO interface coupled with the GIO interface by the virtual channel by monitoring an indication associated with an amount of content transmitted from the GIO interface to the remote GIO interface. | 07-30-2009 |
20100095032 | USE OF COMPLETER KNOWLEDGE OF MEMORY REGION ORDERING REQUIREMENTS TO MODIFY TRANSACTION ATTRIBUTES - A method and system of relaxing the ordering of a read completion by setting an ordering attribute in the read completion. The relaxed ordering allows the read completion to bypass pending writes. | 04-15-2010 |
20100260206 | Communicating A Message Request Transaction To A Logical Device - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 10-14-2010 |
20100303079 | METHOD AND APPARATUS FOR ENABLING ID BASED STREAMS OVER PCI EXPRESS - A method and apparatus for enabling ID based streams over Peripheral Component Interconnect Express (PCIe) is herein described. In this regard an apparatus is introduced including a memory ordering logic to order packets to be transmitted over a serial point-to-point interconnect, the memory ordering logic to bypass a stalled first packet with a second packet that arrived after the first packet if the second packet includes an attribute flag set to indicate that the second packet is order independent and if the second packet includes an ID that is different from an ID associated with the first packet. Other embodiments are also described and claimed. | 12-02-2010 |
20110072164 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 03-24-2011 |
20110161703 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 06-30-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110208925 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 08-25-2011 |
20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
20120036293 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 02-09-2012 |
20120089750 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-12-2012 |
20120096212 | USE OF COMPLETER KNOWLEDGE OF MEMORY REGION ORDERING REQUIREMENTS TO MODIFY TRANSACTION ATTRIBUTES - A method and system of relaxing the ordering of a read completion by setting an ordering attribute in the read completion. The relaxed ordering allows the read completion to bypass pending writes. | 04-19-2012 |
20120254563 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 10-04-2012 |
20130114602 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 05-09-2013 |
20130117474 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 05-09-2013 |
20130117490 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 05-09-2013 |
20130145049 | MECHANISM FOR CLOCK SYNCHRONIZATION - A method and apparatus for synchronizing time between a master device and a target device arranged across a network, wherein the target device communicates to the master device through a PCIe interconnect includes transmitting a first message at a first time from the master device to the target device, the first message including a message indicator; and receiving a reply message at a subsequent time from the target device to the master device, the reply message including the message indicator. | 06-06-2013 |
20130254451 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 09-26-2013 |
20130254452 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 09-26-2013 |
20130268712 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 10-10-2013 |
20140105108 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 04-17-2014 |
20140105228 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 04-17-2014 |
20140112353 | COMMUNICATING MESSAGE REQUEST TRANSACTION TYPES BETWEEN AGENTS IN A COMPUTER SYSTEM USING MULTIPLE MESSAGE GROUPS - A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type. | 04-24-2014 |
20140115219 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 04-24-2014 |
20140115391 | COMMUNICATING MESSAGE REQUEST TRANSACTION TYPES BETWEEN AGENTS IN A COMPUTER SYSTEM USING MULTIPLE MESSAGE GROUPS - A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type. | 04-24-2014 |
20140129747 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link. | 05-08-2014 |
20140185436 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - A storage device is provided to maintain a value of flow control credits allocated for a device on a channel and flow control logic is provided to receive a flow control signal over a link of an interconnect, the flow control signal indicating flow control credits allocated for the device on the channel. The flow control logic is further to update the value of flow control credits based on activity of the device on the channel. | 07-03-2014 |
20140189174 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 07-03-2014 |
20140304448 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 10-09-2014 |
20150078401 | COMMUNICATING MESSAGE REQUEST TRANSACTION TYPES BETWEEN AGENTS IN A COMPUTER SYSTEM USING MULTIPLE MESSAGE GROUPS - A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type. | 03-19-2015 |
20150082091 | COMMUNICATING MESSAGE REQUEST TRANSACTION TYPES BETWEEN AGENTS IN A COMPUTER SYSTEM USING MULTIPLE MESSAGE GROUPS - A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet header for a message request transaction that include a message group sub-field that indicates one of a plurality of message groups. The packet header also includes a format field that indicates whether the message request packet includes data. The packet header further includes a message code field to indicate a specific message type. | 03-19-2015 |