| Patent application number | Description | Published |
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| 20080201128 | Method and System for Performing Ternary Verification - A method and system for performing ternary verification is disclosed. Initially, a ternary model is generated from a binary model of a logic circuit design. The pairings used to encode the ternary model are then recorded. Next, the number of the recorded gate pairings is reduced by removing all invalid gate pairings. A ternary verification is performed on the ternary model having a reduced number of gate pairings. | 08-21-2008 |
| 20080216029 | METHOD AND SYSTEM FOR PERFORMING TARGET ENLARGEMENT IN THE PRESENCE OF CONSTRAINTS - A method for performing verification is disclosed. The method includes receiving a design, including one or one or more targets, one or more constraints, one or more registers and one or more inputs. A first function of one of the one or more targets over the one or more registers and the one or more inputs is computed. A second function of one or more of the one or more constraints over the one or more registers and the one or more inputs is computed. The inputs of the first function and the second function are existentially quantified. A bounded analysis is performed to determine if the one of the one or more targets may be hit while adhering to the constraints. A preimage of the inputs of the first function and a preimage of the inputs of the second function is existentially quantified to create a synthesizable preimage. The synthesizable preimage is simplified and synthesized to create an enlarged target. Verification of the enlarged target is performed. | 09-04-2008 |
| 20080228694 | PREDICATE SELECTION IN BIT-LEVEL COMPOSITIONAL TRANSFORMATIONS - A method for performing verification includes selecting a first set containing a seed register and adding to a second set a result of a subtraction of a fanout of the first set from a fanin of the first set. A third set is rendered equal to a result of a subtraction of a fanin of the second set from a fanout of the second set, and whether a combination of the first set and the third set is equivalent to the first set is determined. In response to determining that the combination of the first set and the second set is not equivalent to the first set, a min-cut of the first set and the second set containing a minimal set of predicates between a first component and the logic to which the component fans out, wherein the logic is bordered by the second set is returned. | 09-18-2008 |
| 20080229263 | PERFORMING UTILIZATION OF TRACES FOR INCREMENTAL REFINEMENT IN COUPLING A STRUCTURAL OVERAPPROXIMATION ALGORITHM AND A SATISFIABILITY SOLVER - A method, system and computer program product for performing verification are disclosed. The method includes creating and designating as a current abstraction a first abstraction of an initial design netlist containing a first target and unfolding the current abstraction by a selectable depth. A composite target is verified, using a satisfiability solver and, in response to determining that the verifying step has hit the composite target, a counterexample is examined to identify one or more reasons for the first target to be asserted. One or more refinement pairs are built by examining the counterexample and a second abstraction is built by composing the refinement pairs. A new target is built over one or more cutpoints in the first abstraction that is asserted when the one or more cutpoints assume values in the counterexample, and the new target is verified with the satisfiability solver. | 09-18-2008 |
| 20080235637 | METHOD FOR HEURISTIC PRESERVATION OF CRITICAL INPUTS DURING SEQUENTIAL REPARAMETERIZATION - A method, system, and computer program product for preserving critical inputs. According to an embodiments of the present invention, an initial design including one or more primary inputs which cannot be eliminated, one or more primary inputs which can be eliminated, one or more targets, and one or more state elements are received. A cut of said initial design including one or more cut gates is identified, and a relation of one or more values producible to said one or more cut gates in terms of said one or more primary inputs which cannot be eliminated, said one or more primary inputs which can be eliminated and said one or more state elements is computed. Said relation is synthesized to form a gate set, and an abstracted design is formed from said gate set. Verification is performed on said abstracted design to generate verification results. | 09-25-2008 |
| 20080256499 | USING CONSTRAINTS IN DESIGN VERIFICATION - A method for generating a constraint for generating a constraint for use in the verification of an integrated circuit design includes identifying a target in a netlist (N) of the design and creating an overapproximate abstraction (N′) of the netlist. A space state (S′) is created by enumerating the states of N′ from which the identified target may be asserted. A constraint space C′ is then derived from the state space S′, where C′ is the logical complement of S′. The process is repeated for multiple selected targets and the constraint spaces from each iteration are logically ANDed. Creating an overapproximate abstraction may include replacing a sequential gate with a random gate. Identifying a sequential gate may include selecting a target in the netlist, performing underapproximate verification of the target, and, if a spurious failure occurs, selecting a gate further down the fanin chain of the currently selected gate. | 10-16-2008 |
| 20080270086 | PREDICATE-BASED COMPOSITIONAL MINIMIZATION IN A VERIFICATION ENVIRONMENT - A system for performing verification includes a means for: importing a design netlist containing component(s), computing output function(s) for the component(s), generating output equivalent state set(s) from the output function(s), identifying next-state function(s) for the component(s), means for producing image equivalent state set(s) for the next-state function(s), means for classifying output-and-image equivalent state set(s) for the image equivalent state set(s) and the output equivalent state set(s), getting a preimage from the next-state function(s) and the output-and-image equivalent state(s) to generate a preimage of the output-and-image equivalent state(s), partitioning over original state(s) of the component(s), and equivalent class input set(s) of the component(s). Moreover, the system includes a means for: selecting input representative(s) of the equivalent input set(s), forming an input map from the input representative(s), synthesizing the input map, and injecting the input map back into the netlist to generate a modified netlist. | 10-30-2008 |
| 20080307372 | METHOD AND SYSTEM FOR PERFORMING MINIMIZATION OF INPUT COUNT DURING STRUCTURAL NETLIST OVERAPPROXIMATION - A method for performing verification is disclosed. The method includes selecting a set of gates to add to a first localization netlist and forming a refinement netlist. A min-cut is computed with sinks having one or more gates in the refinement netlist and sources comprising one or more inputs of an original netlist and one or more registers registers of the original netlist which are not part of the refinement netlist. A final localized netlist is obtained by adding one or more gates to the refinement netlist to grow the refinement netlist until reaching one or more cut-gates of the min-cut. | 12-11-2008 |
| 20090049416 | Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints - An incremental verification method includes eliminating verification constraints from a first netlist and using the resulting netlist to create a constraint-free composite netlist suitable for determining equivalence between the first netlist and a second netlist of a design. Eliminating a constraint from a netlist may include adding a modified constraint net where the modified constraint net is FALSE for all cycles after any cycle in which the original constraint is FALSE. The method may include, instead of eliminating constraints, determining that the verification result is a target-not-asserted result and that the second netlist constraints are a superset of the first netlist constraints or that the verification result is a target-asserted result and that the first netlist constraints are a superset of the second netlist constraints. In either case, the method may include creating the composite netlist by importing all of the original constraints into the composite netlist. | 02-19-2009 |
| 20090094563 | Method and System for Enhanced Verification By Closely Coupling a Structural Satisfiability Solver and Rewriting Algorithms - A method, system and computer program product are disclosed. The method includes initializing a first variable to limit a rewrite time for rewrite operations with respect to an initial design by a rewriting module, a second variable to limit a time for satisfiability solver operations with respect to said initial design by a satisfiability solver module and a third variable to limit a maximum number of rewrite iterations with respect to said initial design. A timer is called to track said rewrite time and a local logic rewriting operation is run on said initial design with said rewrite module. In response to determining that all of all targets for said initial design netlist are not solved, whether a rewrite time is expired is determined. In response to determining that said rewrite time is not expired, AND refactoring is run. In response to determining that said rewrite time is not expired, XOR refactoring is run. | 04-09-2009 |
| 20090100385 | Optimal Simplification of Constraint-Based Testbenches - Methods and systems are provided for determining redundancies in a system model such as a complex circuit design including gates that are state components. A candidate redundant gate is selected, and a merged model is built that eliminates the candidate redundant gate. If the candidate redundant gate is within the merged constraint cone the pre-merge model is used to validate redundancy of the candidate redundant gate. However, if the candidate redundant gate is not within the merged constraint cone the merged model is instead used to validate redundancy of the candidate redundant gate. | 04-16-2009 |
| 20090138837 | System and Method for Sequential Equivalence Checking for Asynchronous Verification - A system and method for performing sequential equivalence checking for asynchronous verification are provided. A first model of the integrated circuit design is provided that has additional logic in it to reflect the possible variance in behavior of the asynchronous crossings. A second model of the integrated circuit design is provided that does not have this asynchronous behavior logic but instead correlates to the simplest synchronous model that is usually used for non-asynchronous functional verification tasks. Sequential equivalence checking is performed to verify that the two models are input/output equivalent. In order to address non-uniform arrival times of bus strands, logic is provided for identifying bus strands that have transitioning bits, determining a representative delay for these strands, comparing the representative delays for all of the bus strands to determine the maximum delay for the entire bus, and applying this maximum delay to one of the models. | 05-28-2009 |
| 20090300559 | Incremental Speculative Merging - An incremental speculative merge structure which enables the elimination of invalid merge candidates without requiring the discarding of the speculative merge structure and all verification results obtained upon that structure. Targets are provided for validating the equivalence of gates g | 12-03-2009 |
| 20100042965 | Method and System for Scalable Reduction in Registers With Sat-Based Resubstitution - A method, system, and computer program product for reducing the size of a logic network design, prior to verification of the logic network design. The method includes eliminating registers to reduce the size of the logic network design; thereby, increasing the speed and functionality of the verification process, and decreasing the size of the logic network design. The system identifies one or more compatible resubstitutions of a selected register, wherein the compatible resubstitution expresses the selected register as one or more pre-existing registers of fixed initial state. The resubstitutions are refined utilizing design invariants. When one more resubstitutions are preformed, the system eliminates the selected registers to reduce the size of the logic network design. As a result of the resubstitution process, a logic network design of reduced size is generated. | 02-18-2010 |
| 20100185993 | METHOD FOR SCALABLE DERIVATION OF AN IMPLICATION-BASED REACHABLE STATE SET OVERAPPROXIMATION - A method, system and computer program product for integrating implication-based analysis and equivalent gate analysis to maintain transitive reduction in an implication graph over a sequence of graph operations. One or more gates of a design are identified that are equivalent in all reachable states. Equivalent gates are assigned to an equivalence class when all gates within the equivalence class are equal. During the implication-based analysis the system determines when one or more implication paths are associated with the one or more equivalence classes, and an implication is generated at the implication path associated with the equivalence classes. A transitively reduced graph is received depicting the implications and equivalence classes of the design. When one or more operations are assigned to the transitively reduced graph, the graph is automatically adjusted to maintain transitive reduction. | 07-22-2010 |
| 20100199241 | Method and System for Automated Use of Uninterpreted Functions in Sequential Equivalence Checking - A method, system and computer program product for automated use of uninterpreted functions in sequential equivalence checking. A first netlist and a second netlist may be received and be included in an original model, and from the original model, logic to be abstracted may be determined. A condition for functional consistency may be determined, and an abstract model may be created by replacing the logic with abstracted logic using one or more uninterpreted functions. One or more functions may be performed on the abstract model. For example, the one or more functions may include one or more of a bounded model checking (BMC) algorithm, an interpolation algorithm, a Boolean satisfiability-based analysis algorithm, and a binary decision diagram (BDD) based reachability analysis algorithm, among others. | 08-05-2010 |
| 20100218148 | Method and System for Sequential Netlist Reduction Through Trace-Containment - Methods and systems are provided for sequential netlist reduction through trace-containment for a circuitry design netlist by first identifying a cut of the netlist and enumerating a set of mismatch traces. Perform time-bounded unfolding of a cofactored version of the cut to reflect the sequential cofactor for a specific input i and temporal uncorrelation constraints for the set of inputs ‘J’. Determine whether there is trace containment by performing equivalence checking with respect to the cut of the netlist under temporal uncorrelation constraints for the set of inputs ‘J’. In response to detecting trace containment, simplify the netlist by merging the input ‘i’ to a constant. | 08-26-2010 |
| 20100251197 | METHOD, SYSTEM AND APPLICATION FOR SEQUENTIAL COFACTOR-BASED ANALYSIS OF NETLISTS - Methods, systems and computer products are provided for reducing the design size of an integrated circuit while preserving the behavior of the design with respect to verification results. A multiplexer is inserted at the gate being analyzed, and the multiplexer selector is controlled to provide a predetermined output for one frame at the point being analyzed. It is then determined whether the circuit remains equivalent during application of the predetermined output in order to decide whether the gate being analyzed is a candidate for replacement. | 09-30-2010 |
| 20100251199 | Method and system for automated convergence of ternary simulation by saturation of deep gates - A method, system and computer program product for X-Saturated ternary simulation based reduction. An X-Saturated ternary simulation (XSTS) utility, which executes on a computer system, receives design information, where the design information includes a netlist. The XSTS utility initializes one or more data structures and/or variables and simulates, in a ternary fashion, the netlist at a time value by applying logical X values to all RANDOM gates of the netlist and to registers marked X_SATURATED. For each register of the netlist XSTS utility: determines whether or not the register departs from its expected prefix behavior, and if the register departs from its expected prefix behavior, the register is marked as X_SATURATED and the current state is updated with an X value upon the register. XSTS utility can store the current state in a data structure and can use the information from the data structure to simplify the design. | 09-30-2010 |
| 20100269077 | Trace Containment Detection of Combinational Designs via Constraint-Based Uncorrelated Equivalence Checking - Methods and systems are provided for producing more efficient digital circuitry designs by identifying trace-containment for a sequential circuitry design netlist through the use of constraint-based uncorrelated equivalence checking. A set of candidate input netlist sets n | 10-21-2010 |
| 20110093824 | TECHNIQUES FOR PERFORMING CONDITIONAL SEQUENTIAL EQUIVALENCE CHECKING OF AN INTEGRATED CIRCUIT LOGIC DESIGN - A technique for conditional sequential equivalence checking of logic designs embodied in netlists includes creating an equivalence-checking netlist over a first netlist and a second netlist. The conditional sequential equivalence checking includes conditions under which equivalences of the first and second netlists are checked. The technique derives a set of candidate conditional equivalence invariants for each correlated gate in a correlated gate pair set and attempts to prove that each candidate conditional equivalence invariant in the set of candidate conditional equivalence invariants is accurate. The candidate conditional equivalence invariants that cannot be proven accurate are removed from the set of candidate conditional equivalence invariants. The candidate conditional equivalence invariants that have been proven accurate are recorded as a set of conditional equivalence invariants. Finally, the conditional sequential equivalence checking of the equivalence-checking netlist is completed using the set of conditional equivalence invariants that are recorded. | 04-21-2011 |
| 20110093825 | TECHNIQUES FOR ANALYSIS OF LOGIC DESIGNS WITH TRANSIENT LOGIC - A technique for performing an analysis of a logic design includes detecting an initial transient behavior in a logic design embodied in a netlist. A duration of the initial transient behavior is also determined. Reduction information on the logic design is gathered based on the initial transient behavior. The netlist is then modified based on the reduction information. | 04-21-2011 |
