| Patent application number | Description | Published |
|---|
| 20110051502 | Flexible Word-Line Pulsing For STT-MRAM - A method for generating a variable pulse width signal on an integrated circuit (IC) chip, includes receiving a first clock signal on the IC chip and receiving a second clock signal on the IC chip having a variable delay relative to the first clock signal. A signal having a rising edge triggered by a rising edge of the first clock signal and a falling edge triggered by a rising edge of the second clock signal is output. The output signal is provided to circuitry on the chip, such as a magnetoresistive junction (MTJ) cell of a spin torque transfer magnetic random access memory (STT-MRAM). | 03-03-2011 |
| 20110051509 | System and Method to Manufacture Magnetic Random Access Memory - A system and method to manufacture magnetic random access memory is disclosed. In a particular embodiment, a method of making a magnetic tunnel junction memory system includes forming a portion of a metal layer into a source line having a substantially rectilinear portion. The method also includes coupling the source line, at the substantially rectilinear portion, to a first transistor using a first via. The first transistor is configured to supply a first current received from the source line to a first magnetic tunnel junction device. The method includes coupling the source line to a second transistor using a second via, where the second transistor is configured to supply a second current received from the source line to a second magnetic tunnel junction device. | 03-03-2011 |
| 20110170338 | System and Method to Control A Direction of a Current Applied to a Magnetic Tunnel Junction - A system and method to control a direction of a current applied to a magnetic tunnel junction is disclosed. In a particular embodiment, an apparatus comprises a magnetic tunnel junction (MTJ) storage element and a sense amplifier. The sense amplifier is coupled to a first path and to a second path. The first path includes a first current direction selecting transistor and the second path includes a second current direction selecting transistor. The first path is coupled to a bit line of the MTJ storage element and the second path is coupled to a source line of the MTJ storage element. | 07-14-2011 |
| 20110194333 | System and Method to Select a Reference Cell - A system and method to select a reference cell is disclosed. In a particular embodiment, a method is disclosed that includes receiving an address corresponding to a bit cell within a first bank of a memory. The method also includes accessing a second reference cell of a second bank of the memory in response to a first reference cell in the first bank being indicated as bypassed. | 08-11-2011 |
| 20110219266 | System and Method of Testing an Error Correction Module - In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point. | 09-08-2011 |
| 20110228594 | Multi-Port Non-Volatile Memory that Includes a Resistive Memory Element - A system and method to access a multi-port non-volatile memory that includes a resistive memory element is disclosed. In a particular embodiment, a multi-port non-volatile memory device is disclosed that includes a resistive memory cell and multiple ports coupled to the resistive memory cell. | 09-22-2011 |
| 20110228595 | Memory Cell That Includes Multiple Non-Volatile Memories - A system and method to read and write data at a memory cell that includes multiple non-volatile memories is disclosed. In a particular embodiment, a memory device is disclosed that includes a plurality of memory cells, where at least one of the memory cells comprises a first non-volatile memory including a first resistive memory element and a second multi-port non-volatile memory including a second resistive memory element. | 09-22-2011 |
| 20110235391 | Reference Cell Write Operations At A Memory - A method of selecting a reference circuit for a write operation is disclosed. The method comprises selecting a reference circuit for a write operation based on an output of a row decode circuit and a column decode circuit. The reference circuit is programmed concurrently with a write operation of at least one of a plurality of memory cells in a memory array without requiring an external reference circuit write command. | 09-29-2011 |
