Hardell
Dave Hardell, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090186527 | MICRODVI CONNECTOR - A small form-factor, high performance connector is disclosed. This connector is intended for use with high bandwidth digital video, implementing differential digital signaling, as well as for high bandwidth analog video. The described connector system performs the function of the Digital Visual Interface (DVI) connector, but in a significantly smaller package. Signal integrity is maintained in the smaller form factor by the expedient assignment of signals to pins so that the pin above or below any signal is not used on that interface, thus reducing the chances for signal crosstalk. The pin shape and spacing are created to match pin lengths and minimize inductance while maintaining the proper impedance up to 2.5 GHz. This connector system also implements a tactile feedback mechanism to aid with cable plug insertion, and incorporates a keying mechanism to prevent reverse-plugging. | 07-23-2009 |
Dave Hardell, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20090173534 | I/O CONNECTORS WITH EXTENDABLE FARADAY CAGE - An apparatus providing one or more I/O connections to a computer. The apparatus includes a Faraday cage generally about a flex cable, or other computing element, that may translate when the I/O ports to the computer are utilized. The embodiment maintains the Faraday cage for the flex cable or element as the I/O port housing opens or closes. | 07-09-2009 |
David A. Hardell, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20090221155 | Board Connector - A card connector that allows a card to be at least partially coplanar with a logic board is described herein. A system having a card at least partially coplanar with a logic board is also disclosed. A card connector that allows at least one longitudinal plane through the logic board to intersect at least a point of the card is also disclosed. The card may be a memory module. | 09-03-2009 |
20110081858 | METHODS AND APPARATUS FOR ENHANCED COEXISTENCE ALGORITHMS IN WIRELESS SYSTEMS - Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described. | 04-07-2011 |
20130182589 | METHODS AND APPARATUS FOR ENHANCED COEXISTENCE ALGORITHMS IN WIRELESS SYSTEMS - Methods and apparatus for mitigating the effects of interference between multiple air interfaces located on an electronic device. In one embodiment, the air interfaces include a WLAN interface and PAN (e.g., Bluetooth) interface, and information such as Receiver Signal Strength Index (RSSI) as well as system noise level information are used in order to intelligently execute interference mitigation methodologies, including the selective application of modified frequency selection, variation of transmitter power, and/or change of operating mode (e.g., from multiple-in multiple-out (MIMO) to single-in, single-out (SISO)) so as to reduce isolation requirements between the interfaces. These methods and apparatus are particularly well suited to use cases where the WLAN interface is operating with high data transmission rates. Business methods associated with the foregoing technology are also described. | 07-18-2013 |
20140307889 | ADAPTIVE VIBRATION DAMPING MECHANISM TO ELIMINATE ACOUSTIC NOISE IN ELECTRONIC SYSTEMS - A system to eliminate acoustic noise caused by a first MLCC (Multi-Layer Ceramic Capacitor) array positioned on a PCB (printed circuit board) is disclosed. The first MLCC array generates a first vibration responsible for the acoustic noise in response to receiving a varying input voltage. A third MLCC array senses the first vibration and generates a feedback signal. An adaptive filter then uses the feedback signal to generate an output signal that is used by a second MLCC to generate a second vibration that acts as a counter to dampen the first vibration. Because the input voltage signal is varying in time, the adaptive filter continually samples the varying input voltage and the feedback signal to generate the output signal that minimizes the acoustic noise. The second and third MLCC arrays are selectively positioned and oriented on the PCB for optimum performance. | 10-16-2014 |
Thomas Jason Hardell, Point Pleasant, NJ US
Patent application number | Description | Published |
---|---|---|
20090194009 | BUMPER ASSEMBLIES FOR MODULAR BARGES AND METHODS THEREFOR - A system for protecting a modular barge, which includes a plurality of modular barge sections assembled together using male and female connections, is provided. Each modular barge section has a top surface, a bottom surface, a side wall extending between the top and bottom surfaces, and at least one male connector projecting from the side wall. Some of the male connectors are exposed at an outer peripheral of the barge. A bumper is coupled with the at least one exposed male connector. The bumper extends between the top and bottom surfaces of the modular barge section to which it is attached. | 08-06-2009 |
Wesley D. Hardell, San Antonio, TX US
Patent application number | Description | Published |
---|---|---|
20090240928 | CHANGE IN INSTRUCTION BEHAVIOR WITHIN CODE BLOCK BASED ON PROGRAM ACTION EXTERNAL THERETO - Extended, alternate and/or modified instruction behavior can be established using a program construct that appears outside a bounded block of program code in such a way that the behavioral changes are limited to the bounded block and coincide with a particular point in the execution thereof. These extensions, alternations and/or modifications are supported in some processor embodiments in ways that add neither additional code space nor additional execution cycles to the bounded block. In general, the particular point in execution of the bounded block may be specified in a variety of ways, including positionally or temporally. Techniques described herein have broad applicability, but will be understood by persons of ordinary skill in the art in the context of certain illustrative code blocks, including zero- (or low-) overhead loops, lightweight procedures and very long instruction word (VLIW) type instruction packets, and processors that support them. | 09-24-2009 |