| Patent application number | Description | Published |
|---|
| 20090040851 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily. | 02-12-2009 |
| 20090092000 | SEMICONDUCTOR MEMORY DEVICE WITH REDUCED CURRENT CONSUMPTION - A semiconductor memory device includes memory blocks, a main word decoder to set a main word line to a first potential for activation, a second potential, or a third potential, a circuit to generate a cyclic signal that indicates timing at intervals, a block selecting circuit to select a memory block to be accessed, a successive-selection circuit to select the memory blocks one after another, and a circuit configured to control the main word decoder such that unselected ones of the main word lines of a memory block selected by the block selecting circuit are set to the third potential, such that the main word lines of the selected memory block are maintained at the third potential after access, and such that the main word lines of a memory block selected by the successive-selection circuit are set to the second potential at the timing indicated by the cyclic signal. | 04-09-2009 |
| 20090190416 | SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of the plurality of control-signal pads. The switch circuit generates a first control signal to be supplied to the timing control circuit based on a signal from the input-signal pad in a first mode. | 07-30-2009 |
| 20090245012 | SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM - A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a pulse width of the first signal. | 10-01-2009 |
| Patent application number | Description | Published |
|---|
| 20100020973 | TRANSMISSION DEVICE AND RECEPTION DEVICE FOR CIPHERING PROCESS - In a wireless communication system, a transmission device includes: a generation section configured to encrypt information shared between the transmission device and a reception device using first encryption information which changes in accordance with the sequence information, and to generate encrypted data for the shared information; a transmission section configured to transmit, to the reception device, the encrypted data for the shared information; a reception section configured to receive, from the reception device, information about a result of a comparison between the shared information and a result of decrypting the encrypted data for the shared information using second encryption information which changes in accordance with the sequence information assigned to the encrypted ciphering-process-target data at the reception device; and a determination section configured to determine, based on the comparison result, whether the first and second encryption information matches or not. | 01-28-2010 |
| 20100080195 | MOBILE COMMUNICATION SYSTEM - A mobile communication system including a plurality of base stations includes a radio communicator for communicating with mobile terminal devices with a plurality of carriers, and a communication controller for changing radio field intensity of the radio communicator; and a management device including: a storage for storing information of each of the base stations, the information including time slots and a number of registration requests from the mobile terminal devices in each communication area of the base station in accordance with the time slots, and an instructor for instructing to change radio field intensity of the plurality of carriers to the radio communicator in the base stations on the bases of the stored information in the storage when the number of the registration requests in the time slot exceed a specified predetermined threshold value. | 04-01-2010 |
| Patent application number | Description | Published |
|---|
| 20090049336 | PROCESSOR CONTROLLER, PROCESSOR CONTROL METHOD, STORAGE MEDIUM, AND EXTERNAL CONTROLLER - A processor having a plurality of hardware resources can perform separate controls within a proper range according to the dependent relations of hardware resources troubled. In case a notification is made of the failure of the hardware resources constituting the processor, a processor control method decides the range of the hardware resources, which cannot be used because of that failure, as a failure range, on the basis of the dependencies of the individual hardware resources predetermined, and stops the use of the hardware resources of the failure range on the basis of that decision result. When the use of the hardware resources indicated by the failure range is stopped, the hardware is not stopped before a predetermined operation is performed not to affect the instruction processing procedure outside of the failure range. | 02-19-2009 |
| 20100242025 | PROCESSING APPARATUS AND METHOD FOR ACQUIRING LOG INFORMATION - A processing apparatus, which contains a processor that executes a program includes a series of instructions, includes a log recording unit configured to record an operation log of the processing apparatus; a managing unit configured to control a recording operation performed by the log recording unit and read the operation log recorded in the log recording unit; an input unit configured to detect, from among the series of instructions of the executed program; a start instruction that starts a process for delivering a control instruction destined for the managing unit to the managing unit and deliver the control instruction to the managing unit in response to the start instruction; and an output unit configured to receive the operation log read by the managing unit. | 09-23-2010 |
| Patent application number | Description | Published |
|---|
| 20090122438 | DESIGN OF FEEDFORWARD CONTROLLER FOR CONTROLLING POSITION OF MAGNETIC HEAD IN MAGNETIC DISK DRIVE - For a feedforward controller for controlling a position of a magnetic head in a magnetic disk drive, a vibration of the magnetic head is measured in a state in which a magnetic disk is rotated in the magnetic disk drive. From a spectrum of the measured vibration, a flutter frequency which is a frequency of a vibration caused by the magnetic disk fluttering is obtained. A filter is designed for each flutter frequency having a peak of a gain for a respective one of obtained flutter frequencies. The feedforward controller for controlling a position of the magnetic head is obtained by combining filters designed for the respective flutter frequencies. | 05-14-2009 |
| 20090296263 | INFORMATION STORAGE APPARATUS - An information storage apparatus includes a disc-shaped recording medium in which control marks aligned in a predetermined rule are recorded, a head contacting or approaching a recording medium surface to reproduce/record information of the recording medium and detecting the control marks, a head driving section holding the head to move the head in a direction of coming near or away to/from a recording medium rotation center, a driving force control section controlling a driving force for head driving section, a driving time control section controlling a driving time for the head driving section using an interval of the detection of the plural control marks as a time unit, and a driving force correcting section obtaining a difference between an ideal interval based on the rule of the control marks and an actual interval of the control marks to correct the control of the driving force based on the difference. | 12-03-2009 |
| 20100134913 | FREQUENCY CONTROL APPARATUS AND STORAGE DEVICE - According to one embodiment, a frequency control apparatus includes an eccentric component storage module, a frequency correction amount calculating module, and an oscillator control module. The eccentric component storage module stores in advance an eccentric component calculated by a discrete Fourier transform of the number of clock signals measured for each servo frame. The frequency correction amount calculating module calculates the number of clock signals corresponding to the servo frame based on the eccentric component stored in the eccentric component storage module and calculates a frequency correction amount corresponding to the servo frame based on the number of clock signals. The oscillator control module controls the operation of a frequency oscillator such that a frequency for oscillating a clock signal in the frequency oscillator is adjusted according to the frequency correction amount calculated by the frequency correction amount calculating module. | 06-03-2010 |
