| Patent application number | Description | Published |
|---|
| 20090256597 | POWER-ON RESET CIRCUIT - A power-on reset circuit according to an embodiment of the present invention includes an input control unit configured to generate a default input signal in response to a power-on reset signal and a clock, a counting unit configured to perform a counting operation in response to the default input signal to generate a count offset signal, and a power-on reset unit configured to perform a counting operation in response to the count offset signal to generate the power-on reset signal. | 10-15-2009 |
| 20100272197 | OFDM SYSTEM AND DATA TRANSMISSION METHOD THEREFOR - An OFDM system includes a frequency-time transformer configured to receive and transform input data to be transmitted to a time-domain sequence; a serial/parallel transformer configured to divide the time-domain sequence into plural sequences; a phase rotating module configured to perform phase rotation in respects to each of the divided time-domain sequences; and a minimum PAPR signal selector configured to select a sequence having a minimum peak-to-average power ratio (PAPR) among the sequences outputted from the phase rotating module. | 10-28-2010 |
| 20100274996 | MICRO-PROCESSOR - A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock. | 10-28-2010 |
