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Hao-Jan
Hao-Jan Chao, Taoyuan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100138709 | METHOD AND APPARATUS FOR DELAY FAULT COVERAGE ENHANCEMENT - A hybrid clocking scheme for simultaneously detecting a b-cycle path-delay fault in a b-cycle (false) path and a c-cycle path-delay fault in a c-cycle (false) path using at least n+1 at-speed clock pulses during a capture operation in a clock domain in a scan design or a scan-based BIST design, where 1<=b<=c<=n. The scan design or BIST design includes multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The design includes one or more clock domains each running at its intended operating frequency or at-speed. The hybrid clocking scheme comprises at least one at-speed shift clock pulse or one at-speed capture clock pulse immediately followed by at least two at-speed capture clock pulses during the capture operation to simultaneously detect the b-cycle path-delay fault and the c-cycle path-delay fault within the clock domain. | 06-03-2010 |
| 20100287430 | MULTIPLE-CAPTURE DFT SYSTEM TO REDUCE PEAK CAPTURE POWER DURING SELF-TEST OR SCAN TEST - A method for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in scan-test or self-test mode, where N>1, each clock domain having one capture clock and a plurality of scan cells, each capture clock comprising a plurality of capture clock pulses; said method comprising: (a) generating and shifting-in N test stimuli to all said scan cells within said N clock domains in said integrated circuit or circuit assembly during a shift-in operation; (b) applying an ordered sequence of capture clocks to all said scan cells within said N clock domains, the ordered sequence of capture clocks comprising at least a plurality of capture clock pulses from two or more selected capture clocks placed in a sequential order such that all clock domains are never triggered simultaneously during a capture operation; and (c) analyzing output responses of all said scan cells to locate any faults therein. | 11-11-2010 |
Hao-Jan Chao, Taoyuan TW
| Patent application number | Description | Published |
|---|---|---|
| 20090132880 | Multiple-capture DFT system for detecting or locating crossing clock-domain faults during self-test or scan-test - A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus. | 05-21-2009 |
Hao-Jan Chen, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090187735 | MICROCONTROLLER HAVING DUAL-CORE ARCHITECTURE - A microcontroller having dual-core architecture is provided. Using a unique hardware configuration of memories, control registers and reset machines, the invention not only reduces hardware cost, but also improves management efficiency and system stability. | 07-23-2009 |
Hao-Jan Chiang, Tamshui Chen TW
| Patent application number | Description | Published |
|---|---|---|
| 20110080301 | POWERLINE NETWORK SYSTEM HAVING DATA RELAY FUNCTION - A powerline network system having data relay function includes a plurality of power monitoring zones mutually connected with a powerline network and at least one repeater. Each of the power monitoring zones has at least one power monitoring device. The repeater is connected with each power monitoring device in two adjacent power monitoring zones through powerlines and has a first and a second relay units. The first and second relay units employ two different sets of transmitting and receiving bands to fetch data contained in powerline signals transmitted by each power monitor in adjacent power monitoring zones. The data are received by a relay unit are modulated with different transmitting band and then transmitted to powerlines of another power monitoring zone. The repeaters are not required to be serially connected to the powerlines, and incorrect data read can be also eliminated. | 04-07-2011 |
Hao-Jan Huang, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100164998 | DRIVING METHOD AND DISPLAY DEVICE CAPABLE OF ENHANCING IMAGE BRIGHTNESS AND REDUCING IMAGE DISTORTION - A driving method for a display device provides a first input pixel data corresponding to a pixel, and generates a second input pixel data by multiplying the first input pixel data by a predetermined rate. Next, an output pixel data corresponding to the second input pixel data is obtained from a predetermined gamma curve. When receiving the first input pixel data, the output pixel data is used for driving a display panel, and the second input pixel data is used for driving a backlight module of the display panel, | 07-01-2010 |
| 20100207963 | GAMMA VOLATGE GENERATING APPARATUS AND GAMMA VOLTAGE GENERATOR THEREOF - A gamma voltage generator including an operation amplifier, a first reference impedance unit, a second reference impedance unit, a first variable impedance unit, a second variable impedance unit, and a select unit is provided. The operation amplifier generates an amplified output voltage. The first reference impedance unit receives a first gamma voltage, and the second reference impedance unit receives a second gamma voltage. The first variable impedance unit provides a first variable impedance, and the second variable impedance unit receives the first gamma voltage and provides a second variable impedance. The select unit selects the amplified output voltage or the first gamma voltage according to a control signal to generate an interpolated gamma output voltage. | 08-19-2010 |
| 20110115821 | Control Method, Control Device and Electronic Device - A control method for an electronic device includes detecting a distance between an object and a reference point of the electronic device, and generating a control command for the electronic device according to the distance between the object and the reference point, in order to control the electronic device to perform a corresponding function. | 05-19-2011 |
Hao-Jan Kuo, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080303980 | Optical Film with Surface Structure - An optical film with a surface structure includes one surface of a substrate comprising a plurality of light control elements with their longitudinal axes arranged approximately parallel to each other, in which each element includes an independent peak formed by two inclined faces and the two inclined faces between each two independent peaks are connected to each other to form an independent valley; heights of the independent peaks are periodically varied; a virtual connecting line of summits of the independent peaks varied from high to low or from low to high is a straight line, a spacing interval between the independent valleys is varied in a geometric ratio with the height of the independent peak. | 12-11-2008 |
Hao-Jan Lin, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090214462 | COCKCROACH JELLY BAIT - The present invention provides jelly bait for carrying insecticide to kill cockroaches. The jelly bait benefits from maintaining its softness for longer periods of time, which results in higher successful rates in luring and then killing cockroaches. The jelly bait can be injected with a syringe into the crevices or cockroach habitats for best effects in eradication of cockroaches. | 08-27-2009 |
Hao-Jan Yang, Yunlin County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100052646 | CURRENT MIRROR WITH IMMUNITY FOR THE VARIATION OF THRESHOLD VOLTAGE AND THE GENERATION METHOD THEREOF - A current mirror with immunity for the variation of threshold voltage includes raising the voltage difference between the gate and the source of a MOS in the current source, and increasing the channel length of the MOS for limiting the generated reference current. | 03-04-2010 |
Hao-Jan Yu, Chungli City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100006886 | HIGH POWER LIGHT EMITTING DIODE CHIP PACKAGE CARRIER STRUCTURE - A high power LED (light-emitting diode) chip package carrier structure is disclosed and comprises a circuit board, a metal plate and a lid. The circuit board has a perforate groove for positioning a chip, and an electrode contact area formed at two sides or border of the perforate groove. The metal plate is positioned beneath the circuit board. The lid is positioned above the circuit board, and has a through groove with a width larger than the width of the perforate groove of the circuit board such that the electrode contact area can be exposed out in the through groove of the lid. Thus, the manufacturing process can be simplified and helpful to the mass production. | 01-14-2010 |
| 20100096642 | PACKAGING STRUTURE FOR HIGH POWER LIGHT EMITTING DIODE(LED) CHIP - The present invention relates to a packaging structure for high-power light emitting diode (LED) chip, comprising a metal plate, insulators and a cover plate. The metal plate comprises a containing slot and isolating slots formed on the surface by working, and the insulators can be embedded in the isolating slot. After forming a hollow slot and notches on the surface of the cover plate by working, the cover plate is combined with the metal plate and insulators and at the same time, the hollow slot and the notches are corresponding to the containing slot and the isolating slots on the metal plate to form a hollowness state, followed by application of surface treatment to form soldering portions and an anti-soldering layer at the bottom of the metal plate. Then the metal plate is cut on both sides along free ends of the insulators so as to generate electrode contacts with positive and negative electrodes, and the surface mount technology (SMT) can be adopted for assembly of the packaging structure of high-power LED chip so as to simplify manufacturing processes, facilitate mass production and achieve separation of electricity from heat, etc. | 04-22-2010 |