Patent application number | Description | Published |
20090159916 | LIGHT SOURCE WITH REFLECTIVE PATTERN STRUCTURE - A light source includes a substrate and a light-emitting unit. The substrate has a pattern structure, which includes a plurality of concave-convex structures. The light-emitting unit is formed on the pattern structure, and has a backlight surface connected to the pattern structure and a light outputting surface disposed opposite the backlight surface. The pattern structure reflects light, which is outputted from the light-emitting unit in a direction toward the backlight surface, to the light outputting surface. | 06-25-2009 |
20090163003 | MANUFACTURING METHOD OF SELF-SEPARATION LAYER - A manufacturing method of a self separation layer includes the steps of: forming a plurality of convex portions on a substrate; growing a main material layer on the convex portions; and separating the main material layer from the substrate. | 06-25-2009 |
20100040859 | Nanostructured thin-film formed by utilizing oblique-angle deposition and method of the same - The present invention discloses a transparent conductive nanostructured thin-film by oblique-angle deposition and method of the same. An electron beam system is utilized to evaporate the target source. Evaporation substrate is disposed on a plurality of adjustable sample stage. Multiple gas control valve and heat source is provided to control the gas flow and temperature within the process chamber. An annealing process is performed after the evaporation to improve the thin-film structure and optoelectronic properties. | 02-18-2010 |
20100261001 | NANOSTRUCTURED THIN-FILM FORMED BY UTILIZING OBLIQUE-ANGLE DEPOSITION AND METHOD OF THE SAME - The present invention discloses a transparent conductive nanostructured thin-film by oblique-angle deposition and method of the same. An electron beam system is utilized to evaporate the target source. Evaporation substrate is disposed on a plurality of adjustable sample stage. Multiple gas control valve and heat source is provided to control the gas flow and temperature within the process chamber. An annealing process is performed after the evaporation to improve the thin-film structure and optoelectronic properties. | 10-14-2010 |
20110024880 | NANO-PATTERNED SUBSTRATE AND EPITAXIAL STRUCTURE - A nano-patterned substrate includes a plurality of nano-particles or nanopillars on an upper surface thereof. A ratio of height to diameter of each of the nano-particles or each of the nanopillars is either greater than or equal to 1. Particularly, a ratio of height to diameter of the nanopillars is greater than or equal to 5. Each of the nano-particles or each of the nanopillars has an arc-shaped top surface. When an epitaxial growth process is applied onto the nano-patterned substrate to form an epitaxial layer, the epitaxial layer has very low defect density. Thus, a production yield of fabricating the subsequent device can be improved. | 02-03-2011 |
20120073641 | Solar cell apparatus having the transparent conducting layer with the structure as a plurality of nano-level well-arranged arrays - The invention discloses an apparatus for enhancing light absorption of solar cells and photodetectors by diffraction. The invention comprises the structure as the plurality of nano-level well-arranged arrays with a plurality of certain defect areas including the shapes of rod, tapered-cone, and cone, which diffracts incident light to oblique angles for light trapping. Surface reflection can also be reduced for either broadband or narrow band spectral absorption. The increased contact area between the transparent conducting layer and photoactive layer is beneficial for current extraction, which increases the internal quantum efficiency (IQE). | 03-29-2012 |
20120217469 | Light emitting semiconductor device - A semiconductor light emitting device is disclosed, which comprises: a substrate having a first surface and a second surface; a first semiconductor conductive layer is disposed on the first surface of the substrate; an insert layer is disposed on the first semiconductor conductive layer; an active layer is disposed on the insert layer; a second semiconductor conductive layer is disposed on the active layer; a first electrode is disposed on the second semiconductor conductive layer; and a second electrode is disposed on the second surface of the substrate, in which the electric of the second electrode is opposite to that of the first electrode. | 08-30-2012 |
20120273752 | LATERAL-EPITAXIAL-OVERGROWTH THIN-FILM LED WITH NANOSCALE-ROUGHENED STRUCTURE AND METHOD FOR FABRICATING THE SAME - The present invention discloses a lateral-epitaxial-overgrowth thin-film LED with a nanoscale-roughened structure and a method for fabricating the same. The lateral-epitaxial-overgrowth thin-film LED with a nanoscale-roughened structure comprises a substrate, a metal bonding layer formed on the substrate, a first electrode formed on the metal bonding layer, a semiconductor structure formed on the first electrode with a lateral-epitaxial-growth technology, and a second electrode formed on the semiconductor structure, wherein a nanoscale-roughened structure is formed on the semiconductor structure except the region covered by the second electrode. The present invention uses lateral epitaxial growth to effectively inhibit the stacking faults and reduce the thread dislocation density in the semiconductor structure to improve the crystallization quality of the light-emitting layer and reduce leakage current. Meanwhile, the surface roughened structure on the semiconductor structure can promote the external quantum efficiency. | 11-01-2012 |
20130146896 | SEMICONDUCTOR OPTICAL DEVICE HAVING AN AIR MEDIA LAYER AND THE METHOD FOR FORMING THE AIR MEDIA LAYER THEREOF - A method for fabricating air media layer within the semiconductor optical device is provided. The step of method includes a substrate is provided, a GaN thin film is formed on the substrate, a sacrificial layer is formed on the GaN thin film, and a nitride-containing semiconductor layer is formed on the sacrificial layer. The semiconductor optical device is immersed with an acidic solution to remove the portion of sacrificial layer to form an air media layer around the residual sacrificial layer. | 06-13-2013 |
20130228810 | SOLID STATE LIGHTING LUMINAIRE AND A FABRICATION METHOD THEREOF - A solid state lighting luminaire, which comprises a solid state light source, an encapsulated structure, and a first phosphor, is provided. The encapsulated structure encapsulates the solid state light source and has an outside illuminating surface. The first phosphor is patterned to cover a portion of the outside illuminating surface for down-converting the illumination from the solid state light source. | 09-05-2013 |
20130342103 | SOLID STATE LIGHTING LUMINAIRE AND A FABRICATION METHOD THEREOF - A solid state lighting luminaire, which comprises a solid state light source, an encapsulated structure, and a first phosphor, is provided. The encapsulated structure encapsulates the solid state light source and has an outside illuminating surface. The first phosphor is patterned to cover a portion of the outside illuminating surface for down-converting the illumination from the solid state light source. | 12-26-2013 |
20140008609 | LIGHT EMITTING DEVICE WITH NANOROD THEREIN AND THE FORMING METHOD THEREOF - A method of fabricating a light emitting device, comprising: providing a substrate; forming an undoped semiconductor layer on the substrate; forming a patterned metal layer on the undoped semiconductor layer; using the patterned metal layer as a mask to etch the undoped semiconductor layer and forming a plurality of nanorods on the substrate; and forming an light emitting stack on the plurality of nanorods to form a plurality of voids between the light emitting stack and the plurality of nanorods. | 01-09-2014 |
20140084238 | NANO-PATTERNED SUBSTRATE AND EPITAXIAL STRUCTURE CROSS-REFERENCE TO RELATED APPLICATION - A nano-patterned substrate includes a substrate and a plurality of nano-structures. The substrate has an upper surface and each of the plurality of nano-structures comprises a semiconductor buffer region and a buffer region formed on the upper surface of the substrate, wherein one of the pluralities of nano-structures has a ratio of height to diameter greater than 1, and an arc-shaped top surface. | 03-27-2014 |
20140356995 | METHOD FOR FABRICATING A LATERAL-EPITAXIAL-OVERGROWTH THIN-FILM LIGHT-EMITTING DIODE WITH NANOSCALE-ROUGHENED STRUCTURE - A method for fabricating a lateral-epitaxial-overgrowth thin-film LED with a nanoscale-roughened structure is provided. The lateral-epitaxial-overgrowth thin-film LED with a nanoscale-roughened structure has a substrate, a metal bonding layer formed on the substrate, a first electrode formed on the metal bonding layer, a semiconductor structure formed on the first electrode with a lateral-epitaxial-growth technology, and a second electrode formed on the semiconductor structure. A nanoscale-roughened structure is formed on the semiconductor structure except the region covered by the second electrode. Lateral epitaxial growth is used to effectively inhibit the stacking faults and reduce the thread dislocation density in the semiconductor structure to improve the crystallization quality of the light-emitting layer and reduce leakage current. Meanwhile, the surface roughened structure on the semiconductor structure can promote the external quantum efficiency. | 12-04-2014 |
Patent application number | Description | Published |
20080305568 | Method for promoting light emission efficiency of LED using nanorods structure - Method for the light emitting diode (LED) having the nanorods-like structure is provided. The LED employs the nanorods are subsequently formed in a longitudinal direction by the etching method and the PEC method. In addition, the plurality of the nanorods is arranged in an array so that provide the LED having much greater brightness and higher light emission efficiency than the conventional LED. | 12-11-2008 |
20100213440 | Silicon-Quantum-Dot Semiconductor Near-Infrared Photodetector - A mesoporous silica having adjustable pores is obtained to form a template and thus a three-terminal metal-oxide-semiconductor field-effect transistor (MOSFET) photodetector is obtained. A gate dielectric of a nano-structural silicon-base membrane is used as infrared light absorber in it. Thus, a semiconductor photodetector made of pure silicon having a quantum-dot structure is obtained with excellent near-infrared optoelectronic response. | 08-26-2010 |
20120256181 | POWER-GENERATING MODULE WITH SOLAR CELL AND METHOD FOR FABRICATING THE SAME - The invention discloses a power-generating module with solar cell and method for fabricating the same. The power-generating module includes a flexible substrate, a circuit and a solar cell. Both of the circuit and the solar cell are formed on the flexible substrate and are connected with each other, such that the solar cell is capable of providing the power needed by the circuit for operation. | 10-11-2012 |
20120273821 | METHOD FOR PATTERNING AN EPITAXIAL SUBSTRATE, A LIGHT EMITTING DIODE AND A METHOD FOR FORMING A LIGHT EMITTING DIODE - A method for patterning an epitaxial substrate includes: (a) forming an etch mask layer over an epitaxial substrate, and patterning the etch mask layer using a patterned cover mask layer to form the etch mask layer into a plurality of spaced apart mask patterns; and (b) etching the epitaxial substrate that is exposed from the mask patterns, and removing the mask patterns such that the epitaxial substrate is formed with a plurality of spaced apart substrate patterns. | 11-01-2012 |
20130228806 | LIGHT EMITTING DEVICE WITH GRADED COMPOSITION HOLE TUNNELING LAYER - A light emitting device with graded composition hole tunneling layer is provided. The device comprises a substrate and an n-type semiconductor layer is disposed on the substrate, in which the n-type semiconductor layer comprises a first portion and a second portion. A graded composition hole tunneling layer is disposed on the first portion of the n-type semiconductor layer. An electron blocking layer is disposed on the graded composition hole tunneling layer. A p-type semiconductor layer is disposed on the electron blocking layer. A first electrode is disposed on the p-type semiconductor layer, and a second electrode is disposed on the second portion of the n-type semiconductor layer and is electrical insulated from the first portion of the n-type semiconductor. The graded composition hole tunneling layer is used as the quantum-well to improve the transport efficiency of the holes to increase the light emitting efficiency of the light emitting device. | 09-05-2013 |
20140264271 | FERROELECTRIC MEMORY DEVICE - A ferroelectric memory device includes a memory layer, made of a silicon-based ferroelectric memory material. The silicon-based ferroelectric memory material includes a mesoporous silica film with nanopores and atomic polar structures on inner walls of the nanopores. The atomic polar structures are formed by asymmetrically bonding metal ions to silicon-oxygen atoms on the inner walls, and the silicon-based ferroelectric memory material includes semiconductor quantum dots, metal quantum dots and metal-semiconductor alloy quantum dots. | 09-18-2014 |
Patent application number | Description | Published |
20130214281 | METHOD OF GROWING A HIGH QUALITY III-V COMPOUND LAYER ON A SILICON SUBSTRATE - The present disclosure involves a method of fabricating a semiconductor device. A surface of a silicon wafer is cleaned. A first buffer layer is then epitaxially grown on the silicon wafer. The first buffer layer contains an aluminum nitride (AlN) material. A second buffer layer is then epitaxially grown on the first buffer layer. The second buffer layer includes a plurality of aluminum gallium nitride (Al | 08-22-2013 |
20130221320 | LED WITH EMBEDDED DOPED CURRENT BLOCKING LAYER - The present disclosure involves an apparatus. The apparatus includes a photonic die structure that includes a plurality of layers. A current blocking layer is embedded in one of the plurality of layers. The current blocking layer is a doped layer. The present disclosure also involves a method of fabricating a light-emitting diode (LED). As a part of the method, an LED is provided. The LED includes a plurality of layers. A patterned mask is then formed over the LED. The patterned mask contains an opening. A dopant is introduced through the opening to a layer of the LED through either an ion implantation process or a thermal diffusion process. As a result of the dopant being introduced, a doped current blocking component is formed to be embedded within the layer of the LED. | 08-29-2013 |
20130240831 | GROWING AN IMPROVED P-GAN LAYER OF AN LED THROUGH PRESSURE RAMPING - The present disclosure involves an apparatus. The apparatus includes a photonic die structure that includes a light-emitting diode (LED) die. The LED die is a vertical LED die in some embodiments. The LED die includes a substrate. A p-doped III-V compound layer and an n-doped III-V compound layer are each disposed over the substrate. A multiple quantum well (MQW) layer is disposed between the p-doped III-V compound layer and the n-doped III-V compound layer. The p-doped III-V compound layer includes a first region having a non-exponential doping concentration characteristic and a second region having an exponential doping concentration characteristic. In some embodiments, the second region is formed using a lower pressure than the first region. | 09-19-2013 |
20150055671 | PHOTONIC DEVICES WITH EMBEDDED HOLE INJECTION LAYER TO IMPROVE EFFICIENCY AND DROOP RATE - The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer. | 02-26-2015 |
Patent application number | Description | Published |
20140077152 | III-V Group Compound Devices with Improved Efficiency and Droop Rate - The present disclosure involves an illumination apparatus. The illumination apparatus includes an n-doped semiconductor compound layer, a p-doped semiconductor compound layer spaced apart from the n-doped semiconductor compound layer, and a multiple-quantum-well (MQW) disposed between the first semiconductor compound layer and the second semiconductor compound layer. The MQW includes a plurality of alternating first and second layers. The first layers of the MQW have substantially uniform thicknesses. The second layers have graded thicknesses with respect to distances from the p-doped semiconductor compound layer. A subset of the second layers located most adjacent to the p-doped semiconductor compound layer is doped with a p-type dopant. The doped second layers have graded doping concentration levels that vary with respect to distances from the p-doped semiconductor layer. | 03-20-2014 |
20140077153 | Photonic Devices with Embedded Hole Injection Layer to Improve Efficiency and Droop Rate - The present disclosure involves a light-emitting device. The light-emitting device includes an n-doped gallium nitride (n-GaN) layer located over a substrate. A multiple quantum well (MQW) layer is located over the n-GaN layer. An electron-blocking layer is located over the MQW layer. A p-doped gallium nitride (p-GaN) layer is located over the electron-blocking layer. The light-emitting device includes a hole injection layer. In some embodiments, the hole injection layer includes a p-doped indium gallium nitride (p-InGaN) layer that is located in one of the three following locations: between the MQW layer and the electron-blocking layer; between the electron-blocking layer and the p-GaN layer; and inside the p-GaN layer. | 03-20-2014 |
20140077224 | Pre-Cutting a Back Side of a Silicon Substrate for Growing Better III-V Group Compound Layer on a Front Side of the Substrate - The present disclosure involves an apparatus. The apparatus includes a substrate having a front side a back side opposite the front side. The substrate includes a plurality of openings formed from the back side of the substrate. The openings collectively define a pattern on the back side of the substrate from a planar view. In some embodiments, the substrate is a silicon substrate or a silicon carbide substrate. Portions of the silicon substrate vertically aligned with the openings have vertical dimensions that vary from about 100 microns to about 300 microns. A III-V group compound layer is formed over the front side of the silicon substrate. The III-V group compound layer is a component of one of: a light-emitting diode (LED), a laser diode (LD), and a high-electron mobility transistor (HEMT). | 03-20-2014 |
20140078757 | High Voltage LED with Improved Heat Dissipation and Light Extraction - The present disclosure involves a lighting apparatus. The lighting apparatus includes a polygon die. The polygon die includes a plurality of light-emitting diodes (LEDs). Each LED includes a plurality of epi-layers, the epi-layers containing a p-type layer, an n-type layer, and a multiple quantum well (MQW) disposed between the p-type layer and the n-type layer. Each LED includes a p-type electrode and an n-type electrode electrically coupled to the p-type layer and the n-type layer, respectively. The polygon die also includes a submount to which each of the LEDs is coupled. The p-type and the n-type electrodes are located between the submount and the epi-layers. The submount contains a plurality of conductive elements configured to electrically couple at least a portion of the plurality of LEDs in series. | 03-20-2014 |