| Patent application number | Description | Published |
|---|
| 20090316491 | NON-VOLATILE MEMORY DEVICES AND METHODS OF ERASING NON-VOLATILE MEMORY DEVICES - In one embodiment, an erase method for a memory including a memory array having at least first and second programmable transistors connected in series, includes restricting flow of electrons from the first programmable transistor into the second programmable transistor during an erase operation. | 12-24-2009 |
| 20100109065 | THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES HAVING SUB-DIVIDED ACTIVE BARS AND METHODS OF MANUFACTURING SUCH DEVICES - Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar. | 05-06-2010 |
| 20100133599 | Nonvolatile memory device and method for fabricating the same - A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes. | 06-03-2010 |
| 20100193861 | Three-Dimensional Memory Device - A three-dimensional semiconductor device includes a semiconductor substrate, vertical channel structures arranged on the semiconductor substrate in a matrix, a P-type semiconductor layer disposed at the semiconductor substrate to be in direct with the vertical channel structures, and a common source line disposed at the semiconductor substrate between the vertical channel structures. The common source line may be in contact with the P-type semiconductor layer. | 08-05-2010 |
| 20100207184 | Semiconductor devices and methods of forming the same - A semiconductor device includes insulating patterns and gate patterns alternately stacked on a substrate; an active pattern on the substrate, which extends upward along sidewalls of the insulating patterns and the gate patterns; data storage patterns interposed between the gate patterns and the active pattern; and a source/drain region disposed in the active pattern between a pair of gate patterns adjacent to each other. | 08-19-2010 |
| 20100213527 | Integrated Circuit Memory Devices Having Selection Transistors with Nonuniform Threshold Voltage Characteristics - Provided is a semiconductor memory device. In the semiconductor memory device, a lower selection gate controls a first channel region that is defined at a semiconductor substrate and a second channel region that is defined at the lower portion of an active pattern disposed on the semiconductor substrate. The first threshold voltage of the first channel region is different from the second threshold voltage of the second channel region. | 08-26-2010 |
| 20100224929 | NONVOLATILE MEMORY DEVICE - A vertical NAND string nonvolatile memory device can include an upper dopant region disposed at an upper portion of an active pattern and can have a lower surface located a level higher than an upper surface of an upper selection gate pattern. A lower dopant region can be disposed at a lower portion of the active pattern and can have an upper surface located at a level lower than a lower surface of a lower selection gate pattern. | 09-09-2010 |
| 20100240205 | METHODS OF FABRICATING THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES USING EXPANSIONS - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. | 09-23-2010 |
| 20100254191 | SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string. | 10-07-2010 |
| 20100258947 | Nonvolatile memory devices - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device may include cell arrays having a plurality of conductive patterns having a line shape three dimensionally arranged on a semiconductor substrate, the cell arrays being separated from one another; semiconductor patterns extending from the semiconductor substrate to cross sidewalls of the conductive patterns; common source regions provided in the semiconductor substrate under a lower portion of the semiconductor patterns in a direction in which the conductive patterns extend; a first impurity region provided in the semiconductor substrate so that the first impurity region extends in a direction crossing the conductive patterns to electrically connect the common source regions; and a first contact hole exposing a portion of the first impurity region between the separated cell arrays. | 10-14-2010 |
| 20100315875 | NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME - Provided is a method of operating a non-volatile memory device. The method includes applying a turn-on voltage to each of first and second string select transistors of a first NAND string, applying first and second voltages to third and fourth string select transistors of a second NAND string, respectively, and applying a high voltage to word lines connected with memory cells of the first and second NAND strings. | 12-16-2010 |
| 20100320528 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - In a three-dimensional semiconductor memory device, the device includes a semiconductor substrate having a recessed region, an active pattern extending in a direction transverse to the recessed region, an insulating pillar being adjacent to the active pattern and extending in the direction transverse to the recessed region, and a lower select gate facing the active pattern and extending horizontally on the semiconductor substrate. The active pattern is disposed between the insulating pillar and the lower select gate. | 12-23-2010 |
| 20100322000 | PROGRAMMING METHODS FOR THREE-DIMENSIONAL MEMORY DEVICES HAVING MULTI-BIT PROGRAMMING, AND THREE-DIMENSIONAL MEMORY DEVICES PROGRAMMED THEREBY - In a method of multiple-bit programming of a three-dimensional memory device having arrays of memory cells that extend in horizontal and vertical directions relative to a substrate, the method comprises first programming a memory cell to be programmed to one among a first set of states. At least one neighboring memory cell that neighbors the memory cell to be programmed to one among the first set of states is then first programmed. Following the first programming of the at least one neighboring memory cell, second programming the memory cell to be programmed to one among a second set of states, wherein the second set of states has a number of states that is greater than the number of states in the first set of states. | 12-23-2010 |
| 20110012189 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes stacked-gate structures including a plurality of cell gate patterns and insulating patterns alternately stacked on a semiconductor substrate and extending in a first direction. Active patterns and gate dielectric patterns are disposed in the stacked-gate structures. The active patterns penetrate the stacked-gate structures and are spaced apart from each other in a second direction intersecting the first direction, and the gate dielectric patterns are interposed between the cell gate patterns and the active patterns and extend onto upper and lower surfaces of the cell gate patterns. The active patterns share the cell gate patterns in the stacked-gate structures. | 01-20-2011 |
| 20110065270 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF FABRICATING THE SAME - A method of forming a semiconductor memory device includes stacking a plurality of alternating first insulating layers and first sacrificial layers on a substrate to form a first multilayer structure, forming a first hole through the first multilayer structure, forming a first semiconductor pattern in the first hole, stacking a plurality of alternating second insulating layers and second sacrificial layers on the first multilayer structure to form a second multilayer structure, forming a second hole through the second multilayer structure to be aligned with the first hole, forming a second semiconductor pattern in the second hole, forming a trench to expose sidewalls of the first and second insulating layers at a side of the first and second semiconductor patterns, removing at least some portions of the first and second sacrificial layers to form a plurality of recess regions, forming an information storage layer along surfaces of the plurality of recess regions, and forming a conductive pattern within each recess region. | 03-17-2011 |
| 20110076819 | Three-dimensional semiconductor memory device and method of fabricating the same - A method of fabricating a semiconductor memory device includes alternately and repeatedly stacking sacrificial layers and insulating layers on a substrate, forming an active pattern penetrating the sacrificial layers and the insulating layers, continuously patterning the insulating layers and the sacrificial layers to form a trench, removing the sacrificial layers exposed in the trench to form recess regions exposing a sidewall of the active pattern, forming an information storage layer on the substrate, forming a gate conductive layer on the information storage layer, such that the gate conductive layer fills the recess regions and defines an empty region in the trench, the empty region being surrounded by the gate conductive layer, and performing an isotropic etch process with respect to the gate conductive layer to form gate electrodes in the recess regions, such that the gate electrodes are separated from each other. | 03-31-2011 |
| 20110115010 | THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE - Provided is a three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device includes a substrate that has a cell array region including a pair of sub-cell regions and a strapping region interposed between the pair of sub-cell regions. A Plurality of sub-gates are sequentially stacked on the substrate in each of the sub-cell regions, and interconnections are electrically connected to extensions of the stacked sub-gates, respectively, which extend into the strapping region. Each of the interconnections is electrically connected to the extensions of the sub-gate which are disposed in the pair of the sub-cell regions, respectively, and which are located at the same level. | 05-19-2011 |
| 20110147801 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 06-23-2011 |
| 20110151667 | Methods of Manufacturing Three-Dimensional Semiconductor Devices and Related Devices - A three-dimensional semiconductor device may include a substrate including wiring and contact regions and a thin film structure on the wiring and contact regions of the substrate. The thin-film structure may include a plurality of alternating wiring layers and inter-layer insulating layers defining a terraced structure in the contact region so that each of the wiring layers includes a contact surface in the contact region that extends beyond others of the wiring layers more distant from the substrate. A plurality of contact structures may extend in a direction perpendicular to a surface of the substrate with each of the contact structures being electrically connected to a contact surface of a respective one of the wiring layers. Related methods are also discussed. | 06-23-2011 |
