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Han-Ting
Han-Ting Chen, Hsin Chu Shien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090136715 | Air damping shockproof structure - An air damping shockproof structure disposed between a hard disk and a system for damping or buffering a shocking or a vibration to the hard disk in the system. The air damping shockproof structure includes a top portion, a side portion, and a bottom portion, and an air chamber array disposed in the top portion. The air chamber array includes a plurality of air chambers, and a plurality of air outlets disposed corresponding to each air chamber respectively. The cross-sectional area of each air outlet is smaller than a cross-sectional area of each air chamber. | 05-28-2009 |
Han-Ting Chen, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090048810 | Computer-implemented system and method for assisting in designing resilient member - The invention provides a computer-implemented system for assisting in designing a resilient member. The computer-implemented system includes a storage module, an interface module and a processing module. The storage module therein stores a plurality of response surface functions which each corresponds to one of a plurality of applicable materials. The interface module receives input of a desired one of the plurality of applicable materials and N desired values of N geometrical parameters. The processing module selects, according to the desired material, one from the plurality of response surface functions stored in the storage module, and estimates at least one mechanical property associated with the resilient member by applying the desired values of the geometrical parameters in the selected response surface function. | 02-19-2009 |
Han-Ting Chou, Atlanta, GA US
| Patent application number | Description | Published |
|---|---|---|
| 20100137249 | COMPOSITIONS FOR REGULATING OR MODULATING QUORUM SENSING IN BACTERIA, METHODS OF USING THE COMPOUNDS, AND METHODS OF REGULATING OR MODULATING QUORUM SENSING IN BACTERIA - The present disclosure encompasses compounds and compositions that are useful as specific AI-2 antagonists for the control of bacterial quorum sensing. Although the AI-2 antagonists according to the present disclosure may not have bactericidal effect, their ability to attenuate virulence, drug resistance, and/or biofilm formation have therapeutic benefits. In addition, the AI-2 antagonists of the present disclosure can also be used as tools to probe bacterial AI-2 functions. The present disclosure also encompasses methods for inhibiting or attenuating microbial virulence, biofilm formation, and drug resistance. The methods are suitable for preventing bacteria from accruing and forming extensive biofilms that may be a health or hygiene hazard or a physical issue, such as in the blockage of water or fuel lines. | 06-03-2010 |
Han-Ting Tsai, Kao Hsiung TW
| Patent application number | Description | Published |
|---|---|---|
| 20110079856 | STRAINED STRUCTURE OF SEMICONDUCTOR DEVICE - The present disclosure provides a semiconductor device that includes a semiconductor substrate, a gate structure disposed on a surface of the substrate, and strained structures disposed in the substrate at either side of the gate structure and formed of a semiconductor material different from the semiconductor substrate. Each strained structure has a cross-sectional profile that includes a first portion that extends from the surface of substrate and a second portion that tapers from the first portion at an angle ranging from about 50° to about 70°. The angle is measured with respect to an axis parallel to the surface of the substrate. | 04-07-2011 |
Han-Ting Tsai, Kaoshiung TW
| Patent application number | Description | Published |
|---|---|---|
| 20110193167 | Self-Aligned Two-Step STI Formation Through Dummy Poly Removal - An integrated circuit structure includes a semiconductor substrate including an active region. A first shallow trench isolation (STI) region adjoins a first side of the active region. A gate electrode of a MOS device is over the active region and the first STI region. A source/drain stressor region of the MOS device includes a portion in the semiconductor substrate and adjacent the gate electrode. A trench is formed in the semiconductor substrate and adjoining a second side of the active region. The trench has a bottom no lower than a bottom of the source/drain region. An inter-layer dielectric (ILD) extends from over the gate electrode to inside the trench, wherein a portion of the ILD in the trench forms a second STI region. The second STI region and the source/drain stressor region are separated from each other by, and adjoining, a portion of the semiconductor substrate. | 08-11-2011 |
| 20110193179 | LIGHTLY DOPED SOURCE/DRAIN LAST METHOD FOR DUAL-EPI INTEGRATION - An integrated circuit device and method for fabricating the integrated circuit device is disclosed. The method involves providing a substrate; forming a gate structure over the substrate; forming an epitaxial layer in a source and drain region of the substrate that is interposed by the gate structure; and after forming the epitaxial layer, forming a lightly doped source and drain (LDD) feature in the source and drain region. | 08-11-2011 |
| 20110223752 | METHOD FOR FABRICATING A GATE STRUCTURE - The present disclosure discloses an exemplary method for fabricating a gate structure comprising depositing and patterning a dummy oxide layer and a dummy gate electrode layer on a substrate; surrounding the dummy oxide layer and the dummy gate electrode layer with a sacrificial layer; surrounding the sacrificial layer with a nitrogen-containing dielectric layer; surrounding the nitrogen-containing dielectric layer with an interlayer dielectric layer; removing the dummy gate electrode layer; removing the dummy oxide layer; removing the sacrificial layer to form an opening in the nitrogen-containing dielectric layer; and depositing a gate dielectric; and depositing a gate electrode. | 09-15-2011 |
| 20110254105 | Strained Semiconductor Device with Recessed Channel - A semiconductor device having a strained channel and a method of manufacture thereof is provided. The semiconductor device has a gate electrode formed over a channel recess. A first recess and a second recess formed on opposing sides of the gate electrode are filled with a stress-inducing material. The stress-inducing material extends into an area wherein source/drain extensions overlap an edge of the gate electrode. In an embodiment, sidewalls of the channel recess and/or the first and second recesses may be along {111} facet planes. | 10-20-2011 |
Han-Ting Tsai, Kun-San Jeng TW
| Patent application number | Description | Published |
|---|---|---|
| 20110291201 | MULTI-STRAINED SOURCE/DRAIN STRUCTURES - The present disclosure provides a semiconductor device. The semiconductor device includes a silicon substrate. The semiconductor device includes first and second regions that are disposed in the substrate. The first and second regions have a silicon compound material. The semiconductor device includes first and second source/drain structures that are partially disposed in the first and second regions, respectively. The semiconductor device includes a first gate that is disposed over the substrate. The first gate has a first proximity to the first region. The semiconductor device includes a second gate that is disposed over the substrate. The second gate has a second proximity to the second region. The second proximity is different from the first proximity. The first source/drain structure and the first gate are portions of a first transistor, and the second source/drain structure and the second gate are portions of a second transistor. | 12-01-2011 |