| Patent application number | Description | Published |
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| 20090147841 | DISTRIBUTED VIDEO CODING APPARATUS AND METHOD CAPABLE OF CONTROLLING ENCODING RATE - There are provided a distributed video coding apparatus and method capable of controlling an encoding rate, the apparatus including: an intra-frame encoder encoding a key frame and outputting a bit stream of the encoded key frame; an encoder rate control (ERC) module calculating a bit rate according to motion complexity of a present Wyner-Ziv (WZ) frame by using a correlation between the motion complexity and the bit rate; and a turbo encoder encoding the present WZ frame by the bit rate calculated at the ERC module and outputting the encoded WZ bit stream. | 06-11-2009 |
| 20090158285 | APPARATUS AND METHOD FOR CONTROLLING RESOURCE SHARING SCHEDULE IN MULTI-DECODING SYSTEM - An apparatus for controlling a resource sharing schedule in a multi-decoding system including a multi-decoder formed of a plurality of resources, the apparatus including: a storage unit storing status information of the resources and information required in controlling the resource sharing schedule; and a controller, when a source resource requests assignment of a target resource, assigning the target resource, outputting information of the target resource to the source resource, and updating statuses of the resources, wherein the apparatus controls the resource sharing schedule while bidirectionally connected to the resources to share the resources between the multi-decoders. Accordingly, it is possible to reduce an overall decoding time and controlling a resource usage schedule. | 06-18-2009 |
| 20100142620 | METHOD OF GENERATING SIDE INFORMATION BY CORRECTING MOTION FIELD ERROR IN DISTRIBUTED VIDEO CODING AND DVC DECODER USING THE SAME - Disclosed is a technique that shifts the position of a motion compensation block by an error of a motion field and then performs motion compensation to estimate a current frame from past and future frames in digital video coding (DVC), thereby enhancing the accuracy of current frame estimation results. | 06-10-2010 |
| 20110149984 | CONFIGURATION MEMORY APPARATUS IN FPGA AND ROUTER SYSTEM USING THE SAME - Disclosed are a configuration memory apparatus and a router system using the same. The configuration memory apparatus includes: a selection unit selecting one of a first external device and a storage unit and receiving data; a register storing input data received from the selection unit; a storage unit storing data received from the register; and an I/O unit controlling transmission and reception of data to and from the register and a second external device. | 06-23-2011 |
| 20110154149 | PARITY GENERATING APPARATUS AND MAP APPARATUS FOR TURBO DECODING - An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit. | 06-23-2011 |
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| 20100165277 | IN-PLANE-SWITCHING MODE LIQUID CRYSTAL DISPLAY DEVICE - An in-plane-switching mode liquid crystal display device is disclosed. The LCD device includes: first and second substrates opposite to each other; a liquid crystal layer interposed between the first and second substrates; a passivation film formed on the first substrate in which a thin film transistor is disposed; pixel and common electrodes arranged alternately with each other; and a first alignment film formed on the pixel and common electrodes. The liquid crystal layer and the passivation film are formed to have lower non-resistances than that of the first alignment film. | 07-01-2010 |
| 20110051066 | Apparatus and method of fabricating alignment layer for liquid crystal display - Disclosed are an apparatus and method for fabricating an alignment layer for liquid crystal displays, capable of shortening process time, preventing scratches of alignment layers and decreasing black luminance. The method includes coating an alignment agent on a substrate, arranging a nano pattern mold with a groove and a protrusion to contact the alignment agent, pre-curing the alignment agent, separating the nano pattern mold from the alignment agent, and hard-curing the alignment agent separated from the nano pattern mold to form an alignment layer. | 03-03-2011 |
| 20110147743 | THIN FILM TRANSISTOR SUBSTRATE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a thin film transistor substrate and a method for fabricating the same, which can shorten a process time, prevent a scratch from taking place at an alignment film, and increase black luminance. The thin film transistor substrate includes a thin film transistor formed on a substrate, a protective film formed to flatten a step of the thin film transistor and have an uneven surface with repetitive projected patterns and recessed patterns, a pixel electrode formed on the protective film to maintain an uneven shape of the protective film, and an alignment film formed both on the protective film and the pixel electrode to maintain the uneven shapes of the protective film and the pixel electrode. | 06-23-2011 |
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| 20100009508 | Methods of fabricating stack type capacitors of semiconductor devices - Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition. | 01-14-2010 |
| 20100240191 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CAPACITOR - A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer. | 09-23-2010 |
| 20110124176 | METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode. | 05-26-2011 |
