| Patent application number | Description | Published |
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| 20080219066 | MEMORY SYSTEM AND METHOD ENSURING READ DATA STABILITY - A memory system and related method of operation are disclosed. The memory system includes a memory configured to generate a data strobe signal including “(n/2)+1” clock signals, where “n” is a number of base data blocks in read data synchronously transferred by the memory during a read operation, and a memory controller configured to receive the read data, receive the data strobe signal, delay the data strobe signal to generate a delayed data strobe signal, and synchronously output “n/2” sampled data blocks to a requesting device in relation to the delayed data strobe signal. | 09-11-2008 |
| 20080256305 | MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE - A multipath accessible semiconductor memory device provides an interfacing function between multiple processors which indirectly controls a flash memory. The multipath accessible semiconductor memory device comprises a shared memory area, an internal register and a control unit. The shared memory area is accessed by first and second processors through different ports and is allocated to a portion of a memory cell array. The internal register is located outside the memory cell array and is accessed by the first and second processors. The control unit provides storage of address map data associated with the flash memory outside the shared memory area so that the first processor indirectly accesses the flash memory by using the shared memory area and the internal register even when only the second processor is coupled to the flash memory. The control unit also controls a connection path between the shared memory area and one of the first and second processors. The processors share the flash memory and a multiprocessor system is provided that has a compact size, thereby substantially reducing the cost of memory utilized within the multiprocessor system. | 10-16-2008 |
| 20080282042 | Multi-path accessible semiconductor memory device with prevention of pre-charge skip - A multiprocessor system includes first and second processors and a multi-path accessible semiconductor memory device including a shared memory area and a pseudo operation execution unit. The shared memory area is accessible by the first and second processors according to a page open policy. The pseudo operation execution unit responds to a virtual active command from one of the first and second processors to close a last-opened page. The virtual active command is generated with a row address not corresponding to any row of the shared memory area. For example, bit-lines of a last accessed row are pre-charged for closing the last-opened page. | 11-13-2008 |
| 20080291727 | Semiconductor memory system having volatile memory and non-volatile memory that share bus, and method of controlling operation of non-volatile memory - Example embodiments relate to a semiconductor memory system which may include a volatile memory and a non-volatile memory that share a common bus, and a method for controlling the operation of the non-volatile memory. The semiconductor memory system may include a non-volatile memory and a memory controller. The non-volatile memory may include a buffer memory that temporarily stores data to be read from or to be written to a memory cell array, and an internal controller. The memory controller may transmits a mode signal to the non-volatile memory in response to a control signal, the control signal corresponds to either a read mode or a write mode to be applied to the non-volatile memory. In response to the mode signal, the internal controller may control the data to be read to be stored in the buffer memory, if the read mode is to be applied, and the internal controller may control the buffer memory to stand-by until a write command is received, if the write mode is to be applied. | 11-27-2008 |
| 20080313418 | SEMICONDUCTOR MEMORY DEVICE HAVING PROCESSOR RESET FUNCTION AND RESET CONTROL METHOD THEREOF - A semiconductor memory device for use in a multiprocessor system includes a shared memory area and a reset signal generator. The shared memory area is accessible by the processors of the multiprocessor system through different ports, and is assigned to a portion of a memory cell array. The reset signal generator is configured to provide a reset enable signal to a processor, predetermined as a slave processor among the multiple processors, for a predetermined time after an initial booting of the multiprocessor system. The reset signal generator also provides a reset disable signal to the slave processor after the predetermined time lapses. | 12-18-2008 |
| 20090019237 | MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE HAVING CONTINUOUS ADDRESS MAP AND METHOD OF PROVIDING THE SAME - A semiconductor memory device for use in a multiprocessor system includes at least two shared memory areas and a row decoder. The at least two shared memory areas are accessible in common by multiple processors of the multiprocessor system through different ports, and assigned based on predetermined memory capacity to a portion of a memory cell array. The row decoder is configured to form a continuous address map for remaining memory portions of the at least two shared memory areas to be dedicated to one port. Each remaining memory portion does not include a corresponding data transfer portion within each shared memory area. | 01-15-2009 |
| 20090024803 | Multipath accessible semiconductor memory device having shared register and method of operating thereof - A semiconductor memory device for use in a multiprocessor system may be provided. A chip size may be controlled, and a design of circuit may be relatively simplified. The semiconductor memory device for use in a multiprocessor system may include at least two shared memory areas commonly accessible by processors of the multiprocessor system through different ports and assigned with a predetermined memory capacity unit to a portion of a memory cell array, a single shared register adapted outside the memory cell array, corresponding to disable areas formed within the shared memory areas, and/or a switching unit for connecting a decoder of a selected shared memory area to the shared register in response to an applied control signal, to match the shared register to the disable area of the selected shared memory area. A shared register may be commonly used in corresponding to a plurality of shared memory areas, thereby reducing or preventing a chip size increase and simplifying a design of the circuit. | 01-22-2009 |
| 20090089487 | MULTIPORT SEMICONDUCTOR MEMORY DEVICE HAVING PROTOCOL-DEFINED AREA AND METHOD OF ACCESSING THE SAME - A multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a specification related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array. | 04-02-2009 |
| 20090089545 | MULTI PROCESSOR SYSTEM HAVING MULTIPORT SEMICONDUCTOR MEMORY WITH PROCESSOR WAKE-UP FUNCTION - A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor. | 04-02-2009 |
| 20090089573 | MULTI PROCESSOR SYSTEM HAVING DIRECT ACCESS BOOT AND DIRECT ACCESS BOOT METHOD THEREOF - A multiprocessor system having a direct access boot operation and a direct access boot method are provided to substantially reduce a boot error of processor that does not provide a memory link architecture in the multiprocessor system. In an embodiment of the invention, a multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including at least one shared memory area, the multiport semiconductor memory device configured to provide access to the at least one shared memory area by the first processor and the second processor; and a non-volatile memory device coupled to the first processor and the second processor, the non-volatile memory device storing a first boot code associated with the first processor and a second boot code associated with the second processor, the multiprocessor system configured to provide the first processor direct access to the non-volatile memory area during a boot operation and indirect access to the non-volatile memory area otherwise. | 04-02-2009 |
| 20090210691 | Memory System and Memory Management Method Including the Same - A booting method of a digital processing having a first processor and a second processor is provided. An interface between the first processor and the outside is stopped. A second processor program code is transmitted to a second memory from a first memory. A second stage loader (SSL) for the first processor is transmitted to a buffer of the second processor from the first memory. A first processor program code is transmitted to the second memory from the first memory under the control of the second processor and an interface between the first processor and the outside is resumed. The first processor program code is downloaded fast into the second memory to decrease booting time of the digital processing system. | 08-20-2009 |
| 20090254698 | MULTI PORT MEMORY DEVICE WITH SHARED MEMORY AREA USING LATCH TYPE MEMORY CELLS AND DRIVING METHOD - A multiport semiconductor memory device includes; first and second port units respectively coupled to first and second processors, first and second dedicated memory area accessed by first and second processors, respectively and implemented using DRAM cells, a shared memory area commonly accessed by the first and second processors via respective first and second port units and implemented using memory cells different from the DRAM cells implementing the first and second dedicated memory areas, and a port connection control unit controlling data path configuration between the shared memory area and the first and second port units to enable data communication between the first and second processors through the shared memory area. | 10-08-2009 |
| 20100153637 | Arbitration for memory device with commands - A plurality of masters arbitrate for access to a shared memory device, such as a SDRAM (synchronous dynamic random access memory), amongst themselves using software and arbitration interfaces. The masters generate additional commands upon arbitration, such as MRS and PALL commands, for prevention of collision of commands, refresh starvation, and/or a missing pre-charge operation in the shared memory device. | 06-17-2010 |
| 20100246247 | Phase-change random access memories, memory devices, memory systems, methods of operating and methods of manufacturing the same - A memory system includes a memory cell array having a plurality of memory sectors. Each memory sector includes a plurality of memory cells. The memory system further includes a controller configured to write data to the memory cell array in response to a writing signal. The controller is further configured to refresh a memory sector among the plurality of memory sectors each time a writing signal is provided. When N (N is a positive integer) memory cells are programmed, a programming current is less than or equal to about 0.75 mA*N. | 09-30-2010 |
| 20110107006 | Multiprocessor system and method thereof - A multiprocessor system and method thereof are provided. The example multiprocessor system may include first and second processors, a dynamic random access memory having a memory cell array, the memory cell array including a first memory bank coupled to the first processor through a first port, second and fourth memory banks coupled to the second processor through a second port, and a third memory bank shared and connected with the first and second processors through the first and second ports, and a bank address assigning unit for assigning bank addresses to select individually the first and second memory banks, as the same bank address through the first and second ports, so that starting addresses for the first and second memory banks become equal in booting, and assigning bank addresses to select the third memory bank, as different bank addresses through the first and second ports, and assigning, through the second port, bank addresses to select the fourth memory bank, as the same bank address as a bank address to select the third memory bank through the first port. | 05-05-2011 |
| 20110134686 | SEMICONDUCTOR DEVICES INCLUDING SENSE AMPLIFIER CONNECTED TO WORD LINE - A semiconductor device includes a plurality of non-volatile memory cells connected between a plurality of word lines and a plurality of bit lines, respectively, and a sense amplifier block for sensing and amplifying a signal of a word line among the plurality of word lines. | 06-09-2011 |
| 20110161578 | SEMICONDUCTOR MEMORY DEVICE PERFORMING PARTIAL SELF REFRESH AND MEMORY SYSTEM INCLUDING SAME - A semiconductor memory device capable of performing a partial self refresh and semiconductor memory system including same is provided. The semiconductor memory device includes: a memory circuit including a memory array; a skip address storage unit storing an address of an excluded region not requiring refresh in the memory array as a skip address; a refresh address generator providing an address of a region of the memory array requiring refresh as a refresh address; and an address comparator receiving and comparing the skip address and refresh address, and providing a refresh control signal to the memory circuit based on the comparison. | 06-30-2011 |
| 20110161647 | BOOTABLE VOLATILE MEMORY DEVICE, MEMORY MODULE AND PROCESSING SYSTEM COMPRISING BOOTABLE VOLATILE MEMORY DEVICE, AND METHOD OF BOOTING PROCESSING SYSTEM USING BOOTABLE VOLATILE MEMORY DEVICE - A bootable volatile memory device comprises a volatile memory area configured to be written to and read from by a host processor, a boot code area configured to store bootstrap code before a boot procedure is performed by the host processor, a first chip select terminal configured to output a signal used as a chip select signal where the host processor performs the boot procedure by reading the bootstrap code from the boot code area, and a second chip select terminal configured to output a signal used as a chip select signal where the host processor writes and reads data to and from the volatile memory area. | 06-30-2011 |
