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Han-Gu
Han-Gu Kang, Gyeong-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20090063405 | Method for Providing Information Using Data Communication Network - The present invention provides a method of providing information using a data communication network. The information provision method supports an information search using a general public index composed of numerals, characters or period based on information about a person or a business, which is to be searched for, and a personally set index composed of numerals, characters or period preferred by a searcher. Accordingly, the present invention is advantageous in that a searcher can more easily and conveniently search for desired information, and be provided with the information, and in that an integrated search system used for both wired and wireless data communication networks can be constructed. | 03-05-2009 |
Han-Gu Kang, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20080319963 | Method for Providing Information in Data Communication Network Using Private Page - Disclosed herein is a method for providing information in a data communication network using a private page. The method includes the steps of (a) a service providing server receiving necessary information from a searcher's terminal through a data communication network, and generating and storing a private page DataBase (DB); (b) the service providing server receiving necessary information from an information provider's terminal through the data communication network, and generating and storing an information provider DB; (c) the service providing server detecting the connection of the searcher's terminal to a private page through the data communication network; (d) the service providing server directly or indirectly receiving a search index with respect to information to be searched for from the searcher's terminal through a search window or a private search menu provided in the private page; and (e) the service providing server extracting an information provider corresponding to the received search index, and then providing information about the extracted information provider to the searcher's terminal or linking the searcher's terminal to a site managed by the extracted information provider. | 12-25-2008 |
Han-Gu Kim, Gyeonggi-Do KR
| Patent application number | Description | Published |
|---|---|---|
| 20100254051 | Overvoltage Protection Circuits that Inhibit Electrostatic Discharge (ESD) and Electrical Overstress (EOS) Events from Damaging Integrated Circuit Devices - An overvoltage protection circuit includes primary and secondary clamping circuits. The primary clamping circuit is configured to sink overvoltage current from a power supply voltage node (e.g., Vdd) to a reference voltage node (e.g., Vss) in response to an overvoltage condition at the power supply voltage node. The secondary clamping circuit, which is electrically coupled to an output of the primary clamping circuit, is configured to sink additional overvoltage current from the power supply voltage node to the reference node in response to detection of a overvoltage flag at the output of the primary clamping circuit. This overvoltage flag may be represented by a transition (e.g., low-to-high or high-to-low) of a signal generated at an output of the primary clamping circuit. | 10-07-2010 |
Han-Gu Kim, Seongnam-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080310061 | Transistor with EOS protection and ESD protection circuit including the same - A transistor with an electrical overstress (EOS) protection may include an active region, a plurality of impurity regions and a conduction pattern. The active region may be formed in a substrate. The impurity regions may be formed in the active region and arranged at a predetermined or given distance with respect to each other. The conduction pattern may be arranged between each of the impurity regions in a meandering shape, and the conduction pattern may include a center portion connected to a ground terminal. Therefore, a transistor with EOS protection, a clamp device, and an ESD protection circuit including the same may increase an on-time of a clamp device and may sufficiently discharge a charge due to the EOS by including a conduction pattern configured with gates that are connected with respect to each other in a meandering shape. | 12-18-2008 |
| 20090080129 | Semiconductor chips having improved electrostatic discharge protection circuit arrangement - A semiconductor chip may include a plurality of pads arranged in at least a first and a second row, and a plurality of protection circuits connected to the plurality of pads. The plurality of protection circuits may include at least one diode. A first protection circuit may be connected to a first pad in the first row of pads, and a second protection circuit may be connected to a second pad in the second row of pads. The first and second protection circuits may be arranged under the first row of pads. | 03-26-2009 |
| 20100208400 | Pad interface circuit and method of improving reliability of the pad interface circuit - The pad interface circuit includes a first stack MOS transistor having a first terminal connected to a pad and a bulk connected to a first supply voltage; a second stack MOS transistor having a first terminal connected to a second terminal of the first stack MOS transistor and a second terminal, a gate terminal, and a bulk that are connected to the first supply voltage; and a voltage level sensing circuit generating a feedback voltage by using a pad voltage applied from the pad. In addition, the feedback voltage is applied to a gate terminal of the first stack MOS transistor. | 08-19-2010 |
| 20100214705 | Electrostatic discharge protection element and electrostatic discharge protection circuit including the same - An electrostatic discharge (ESD) protection element includes a first diode, a second diode, and a poly resistor. The first diode is connected between a first voltage and an input/output (I/O) pad. The second diode is connected between the I/O pad and a second voltage. The poly resistor is formed on the second diode. | 08-26-2010 |