| Patent application number | Description | Published |
|---|
| 20090311845 | One Transistor Memory Cell with Bias Gate - One-transistor (1T) capacitor-less DRAM cells each include a MOS transistor having a bias gate layer that separates a floating body region from a base substrate. The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic “1” is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held. | 12-17-2009 |
| 20100144107 | Semiconductor Memory Device - A memory device comprising a vertical transistor includes a digit line that is directly coupled to the source regions of each memory cell. Because an electrical plug is not used to form a contact between the digit line and the source regions, a number of fabrication steps may be reduced and the possibility for manufacturing defects may also be reduced. In some embodiments, a memory device may include a vertical transistor having gate regions that are recessed from an upper portion of a silicon substrate. With the gate regions recessed from the silicon substrate, the gate regions are spaced further from the source/drain regions and, accordingly, cross capacitance between the gate regions and the source/drain regions may be reduced. | 06-10-2010 |
| 20100252886 | FIN STRUCTURES AND METHODS OF FABRICATING FIN STRUCTURES - There is provided fin structures and methods for fabricating fin structures. More specifically, fin structures are formed in a substrate. The fin structures may include two fins separated by a channel, wherein the fins may be employed as fins of a field effect transistor. The fin structures are formed below the upper surface of the substrate, and may be formed without utilizing a photolithographic mask to etch the fins. | 10-07-2010 |
| 20110012182 | Semiconductor Constructions and Transistors, and Methods of Forming Semiconductor Constructions and Transistors - The invention includes a transistor device having a semiconductor substrate with an upper surface. A pair of source/drain regions are formed within the semiconductor substrate and a channel region is formed within the semiconductor substrate and extends generally perpendicularly relative to the upper surface of the semiconductor substrate. A gate is formed within the semiconductor substrate between the pair of the source/drain regions. | 01-20-2011 |
| Patent application number | Description | Published |
|---|
| 20080290388 | Semiconductor contructions - The invention includes a method in which a semiconductor substrate is provided to have a memory array region, and a peripheral region outward of the memory array region. Paired transistors are formed within the memory array region, with such paired transistors sharing a source/drain region corresponding to a bitline contact location, and having other source/drain regions corresponding to capacitor contact locations. A peripheral transistor gate is formed over the peripheral region. Electrically insulative material is formed over the peripheral transistor gate, and also over the bitline contact location. The insulative material is patterned to form sidewall spacers along sidewalls of the peripheral transistor gate, and to form a protective block over the bitline contact location. Subsequently, capacitors are formed which extend over the protective block, and which electrically connect with the capacitor contact locations. The invention also includes semiconductor constructions. | 11-27-2008 |
| 20080299753 | Peripheral Gate Stacks and Recessed Array Gates - Methods are provided for simultaneously processing transistors in two different regions of an integrated circuit. Planar transistors are provided in a logic region while recessed access devices (RADs) are provided in an array region for a memory device. During gate stack patterning in the periphery, word lines are recessed within the trenches for the array RADs. Side wall spacer formation in the periphery simultaneously provides an insulating cap layer burying the word lines within the trenches of the array. | 12-04-2008 |
| 20090239366 | Method Of Forming A Transistor Gate Of A Recessed Access Device, Method Of Forming A Recessed Transistor Gate And A Non-Recessed Transistor Gate, And Method Of Fabricating An Integrated Circuit - Methods and structures are provided for full silicidation of recessed silicon. Silicon is provided within a trench. A mixture of metals is provided over the silicon in which one of the metals diffuses more readily in silicon than silicon does in the metal, and another of the metals diffuses less readily in silicon than silicon does in the metal. An exemplary mixture includes 80% nickel and 20% cobalt. The silicon within the trench is allowed to fully silicide without void formation, despite a relatively high aspect ratio for the trench. Among other devices, recessed access devices (RADs) can be formed by the method for memory arrays. | 09-24-2009 |
| 20100148249 | Method Of Manufacturing A Memory Device - A memory device comprises an active area comprising a source and at least two drains defining a first axis. At least two substantially parallel word lines are defined by a first pitch, with one word line located between each drain and the source. Digit lines are defined by a second pitch, one of the digit lines being coupled to the source and forming a second axis. The active areas of the memory array are tilted at 45° to the grid defined by the word lines and digit lines. The word line pitch is about 1.5F, while the digit line pitch is about 3F. | 06-17-2010 |
| 20100273303 | Memory Arrays and Methods of Fabricating Memory Arrays - A memory array includes a plurality of memory cells formed on a semiconductor substrate. Individual of the memory cells include first and second field effect transistors respectively comprising a gate, a channel region, and a pair of source/drain regions. The gates of the first and second field effect transistors are hard wired together. A conductive data line is hard wired to two of the source/drain regions. A charge storage device is hard wired to at least one of the source/drain regions other than the two. Other aspects and implementations are contemplated, including methods of fabricating memory arrays. | 10-28-2010 |
| 20110081755 | Methods Of Fabricating An Access Transistor Having A Polysilicon-Comprising Plug On Individual Of Opposing Sides Of Gate Material - Fabrication methods for gate transistors in integrated circuit devices enable the formation of recessed access device structures or FinFET structures having P-type workfunctions. The fabrication methods also provide for the formation of access transistor gates of an access device following formation of the periphery transistor gates. Access devices and systems including same are also disclosed. | 04-07-2011 |
| 20110092062 | Transistor Gate Forming Methods and Transistor Structures - A transistor gate forming method includes forming a metal layer within a line opening and forming a fill layer within the opening over the metal layer. The fill layer is substantially selectively etchable with respect to the metal layer. A transistor structure includes a line opening, a dielectric layer within the opening, a metal layer over the dielectric layer within the opening, and a fill layer over the metal layer within the opening. The metal layer/fill layer combination exhibits less intrinsic less than would otherwise exist if the fill layer were replaced by an increased thickness of the metal layer. The inventions apply at least to 3-D transistor structures. | 04-21-2011 |
