Patent application number | Description | Published |
20080238740 | Methods and systems for calibrating a pipelined analog-to-digital converter - A pipelined analog-to-digital converter includes a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). A method for increasing the accuracy of the pipelined ADC includes calibrating the ADC in each stage of the analog-to-digital converter by adjusting trip points of that ADC. Another method for increasing the accuracy of a pipelined ADC includes measuring error in an output of each the DAC; and correcting an output of the pipelined analog-to-digital converter for the measured error. These methods can be used together to further increase the accuracy of the pipelined ADC. Consequently, a pipelined analog-to-digital converter may include a look-up table containing data for correcting errors in output of each of the DACs, where trip points of the ADCs the ADCs in the stages of the pipelined converter have been calibrated to expected values. | 10-02-2008 |
20090084940 | SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL - A light-to-frequency converter includes a switch ( | 04-02-2009 |
20090268059 | SENSING LIGHT AND SENSING THE STATE OF A MEMORY CELL - A light-to-frequency converter includes a switch ( | 10-29-2009 |
20100066575 | Methods and Systems for Calibrating a Pipelined Analog-to-Digital Converter - This method increases accuracy of a pipelined analog-to-digital converter comprising a plurality of stages, each stage comprising an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The method includes calibrating each the ADC starting from a least significant stage until all ADCs have been calibrated using a reference digital-to-analog converter, the reference digital-to-analog converter selectively outputting values at desired trip points for each the ADC; measuring an output of each the DAC using downstream stages of the pipelined analog-to-digital converter to produce output measurements; and using the output measurements to calculate an error-corrected output of the pipelined analog-to-digital converter. The trip points are adjusted by modifying a reference current input to a comparator of each the ADC. | 03-18-2010 |
20100295714 | Pipelined Analog-to-Digital Converter - A pipelined Analog-to-Digital Converter (ADC) comprising a number of stages, at least one of the stages includes a sample and hold circuit. The sample and hold circuit includes a first output connected to an input of a sub-ADC, an output of the sub-ADC connected to an input of a Digital-to-Analog Converter (DAC), an output of the DAC connected to a node, and a second output connected to the node. The sample and hold circuit is configured to independently scale a signal produced by the first output and a signal produced by the second output. | 11-25-2010 |
20100321227 | Current Mode Analog-to-Digital Converter - A current-mode analog-to-digital converter includes: a current input node; a current-mode sample and hold circuit configured to output a steady source of electrical current having an analog value proportional to a sampled analog value of an electrical current at the current input node; and at least one current comparator that compares the electrical current output by the current-mode sample and hold circuit to at least one reference current to produce a digital representation of the sampled analog value of the electrical current at the current input node. | 12-23-2010 |
20120133539 | Comparator Circuit - An analog-to-digital converter includes a comparator configured to receive a first input signal and a second input signal, in which at least one of the input signals is received between two transistors, each of the transistors being in common-gate configuration. | 05-31-2012 |
20130120066 | REFERENCE BUFFER AMPLIFIER - A reference buffer amplifier within an integrated circuit includes a first output terminal connected to a first bond pad, the first bond pad being connected to a first external pin of the integrated circuit chip, the first external pin to allow an external capacitance to be connected to the output terminal. The reference buffer further includes a variable, settable resistance sub-circuit connected to a second bond pad, the second bond pad also being connected to the first external pin. The resistance sub-circuit is configured to be set to exhibit a resistance value to critically dampen a response of the reference buffer amplifier. | 05-16-2013 |
20130234870 | PIPELINED ADC STAGE FILTERS - A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range. | 09-12-2013 |
20140152477 | Time Interleaving Analog-to-Digital Converter - A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs. | 06-05-2014 |
20140152478 | RANDOMIZED TIME-INTERLEAVED SAMPLE-AND-HOLD SYSTEM - A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs. | 06-05-2014 |