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Hak-Sun
Hak-Sun Chang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100039599 | THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY - Disclosed is a liquid crystal display capable of high quality image and bright display. Gate signal lines are curved at near switching elements of the liquid crystal display. A pixel area is defined by the gate signal lines and their intersecting data signal lines. Pixel electrodes and common electrodes are disposed along a longitudinal direction of a pixel. A pixel signal and a common signal line is connected to the pixel electrode and the common electrode respectively. A storage capacitor may be formed in the middle of a longitudinal direction of the pixel, or where generally a texture may arise during display. One half of the pixel may be symmetrical with the other half with respect to the storage capacitor. A common signal line may be parallel with the data signal line and be disposed nearer to the data signal line than a pixel signal line. The pixel may be disposed symmetrically with respect to the data signal line therebetween. The pixel shape may also be repeated in the direction of the gate signal line. | 02-18-2010 |
| 20100060828 | LIQUID CRYSTAL DISPLAY - A TFT array panel on which both pixel electrodes and common electrodes are formed and a color filter panel is disposed opposing the array panel, and liquid crystals are interposed therebetween. The liquid crystals are aligned parallel to the two panels and driven by parallel electric field formed between the pixel electrodes and reference electrodes. Polarization films are arranged outsides the two panels, and a quasi-A plate compensation film is arranged between the color filter panel and the polarization film. An LCD according to the present invention includes first and second panels, a common electrode formed within the first or the second panel, a pixel electrode formed within the same panel as the common electrode is formed, a liquid crystal layer interposed between the first and second panels, a lower polarization film arranged under the first panel in which the first polarization film is arranged between the first and the second supporting bodies, and an upper polarization film arranged over the second panel in which the second polarization film is arranged between the third and fourth supporting bodies. Yellow shift in black state is also reduced and contrast ratio of side view is improved by minimizing Rth in supporting films or by using TEG polarization film having small Rth. | 03-11-2010 |
Hak-Sun Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100112768 | METHOD OF MANUFACTURING NON-VOLATILE SEMICONDUCTOR DEVICES - A non-volatile semiconductor device includes a memory cell in a first area of a substrate, a low voltage transistor in a second area of the substrate, and a high voltage transistor in a third area of the substrate. The memory cell includes a tunnel insulation layer formed on the substrate, a charge trapping layer pattern formed on the tunnel insulation layer in the first area of the substrate, a blocking layer pattern formed on the charge trapping layer pattern and a control gate formed on the blocking layer pattern. The control gate has a width substantially smaller than a width of the blocking layer pattern and the width of the control gate is substantially smaller than a width of the charge trapping layer pattern. In addition, an offset is formed between the control gate and the blocking layer pattern such that a spacer is not formed on a sidewall of the control gate. | 05-06-2010 |
| 20100173469 | METHODS OF MANUFACTURING CHARGE TRAP-TYPE NON-VOLATILE MEMORY DEVICES - Some methods are directed to manufacturing charge trap-type non-volatile memory devices. An isolation layer pattern can be formed that extends in a first direction in a substrate. A recess unit is formed in the substrate by recessing an exposed surface of the substrate adjacent to the isolation layer pattern. A tunnel insulating layer and a charge trap layer are sequentially formed on the substrate. The tunnel insulating layer and the charge trap layer are patterned to form an isolated island-shaped tunnel insulating layer pattern and an isolated island-shaped charge trap layer pattern by etching defined regions of the substrate, the isolation layer pattern, the tunnel insulating layer, and the charge trap layer until a top surface of the charge trap layer that is disposed on a bottom surface of the recess unit is aligned with a top surface of the isolation layer pattern. A blocking insulating layer is formed that covers the charge trap layer pattern, the isolation layer pattern, and a defined region of the substrate interposed between the charge trap patterns. A gate electrode pattern is formed on the blocking insulating layer to face the charge trap layer pattern. This manufacturing process may reduce charge spreading between unit memory cells and/or may prevent/avoid reduction in the breakdown voltage of the blocking insulating layer. | 07-08-2010 |
Hak-Sun Lee, Suwon-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080220611 | Method of forming fine patterns of semiconductor devices using double patterning - A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate. | 09-11-2008 |