| Patent application number | Description | Published |
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| 20080266928 | SEMICONDUCTOR MEMORY DEVICE - This invention provides a semiconductor memory device with enhanced speed performance or enabling timing adjustment reflected in characteristic variation of memory cells, adapted to suppress an increase in the number of circuit elements. A write dummy bit section comprises a first dummy line and a second dummy line corresponding to complementary bit lines and a plurality of first dummy cells formed to be similar in shape to static memory cells, wherein a write current path is coupled between the first dummy line and the second dummy line. In the write dummy bit section, one voltage level is input to the first dummy line through driver MOSFETs in relation to write signal inputs to the static memory cells and a signal change in the second dummy line precharged at the other voltage level is sensed and output. A timing control circuit deselects a word line selected by an output signal from the write dummy bit section. | 10-30-2008 |
| 20090027986 | Semiconductor memory device - The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened. | 01-29-2009 |
| 20090118868 | ROLL PAPER PRINTING APPARATUS - A roll paper printing apparatus includes a transmission source identification unit to identify a transmission source of print data received from a host interface unit, a transmission source information storage unit to store the transmission source information identified by the transmission source identification unit, a transmission source information comparison unit to compare transmission source information of a preceding print job with transmission source information of a print job which is to be printed next, an uncut printed output identification unit to identify an uncut printed output, and an interrupt printing prohibition unit to prohibit printing of the print job which is to be printed next as interrupt printing if the transmission source information of the preceding print job and the transmission source information of the print job which is to be printed next are different when the uncut printed output is identified by the uncut printed output identification unit. | 05-07-2009 |
| 20110044095 | Semiconductor memory device - The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened. | 02-24-2011 |
| 20110157650 | ROLL PAPER PRINTING APPARATUS - A roll paper printing apparatus includes a transmission source identification unit to identify a transmission source of print data received from a host interface unit, a transmission source information storage unit to store the transmission source information identified by the transmission source identification unit, a transmission source information comparison unit to compare transmission source information of a preceding print job with transmission source information of a print job which is to be printed next, an uncut printed output identification unit to identify an uncut printed output, and an interrupt printing prohibition unit to prohibit printing of the print job which is to be printed next as interrupt printing if the transmission source information of the preceding print job and the transmission source information of the print job which is to be printed next are different when the uncut printed output is identified by the uncut printed output identification unit. | 06-30-2011 |
| Patent application number | Description | Published |
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| 20090136844 | Battery Structure, Assembled Battery, and Vehicle Mounting These Thereon - A bipolar battery includes: a bipolar electrode composed, by forming a positive electrode active material layer | 05-28-2009 |
| 20090233164 | BIPOLAR BATTERY - The present invention provides a bipolar battery made by using a polymer gel electrolyte or a liquid electrolyte in an electrolyte layer, which is highly reliable and prevents liquid junction (short circuit) caused by leak out of an electrolyte solution from the electrolyte part. The present invention provides a bipolar battery laminated, in series, with a plurality pieces of bipolar electrodes which is formed with a positive electrode on one surface of a collector, and a negative electrode on the other surface, so as to sandwich an electrolyte layer, characterized by being provided with a separator which retains the electrolyte later, and a seal resin which is formed and arranged at the outer circumference part of a part of the separator where the electrolyte is retained. | 09-17-2009 |
| 20100322022 | SEMICONDUCTOR STORAGE DEVICE - The present invention is directed to realize high-speed operation and low latency of a semiconductor storage device employing the QDR method. A memory cell array, a first buffer, a second buffer, a first circuit, a second circuit, a first DLL circuit, and a second DLL circuit are provided. The first DLL circuit generates a first internal clock signal so as to reduce a phase difference between a first clock signal fetched via the first buffer and the first internal clock signal transmitted to the first circuit. The second DLL circuit generates the second internal clock signal so as to reduce a phase difference between the second clock signal fetched via the second buffer and the second internal clock signal transmitted to the second circuit. With the configuration, input setup and hold time can be shortened, and the frequency of the clock signal can be further increased. | 12-23-2010 |
| Patent application number | Description | Published |
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| 20080253213 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME - A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized. | 10-16-2008 |
| 20090073793 | SEMICONDUCTOR MEMORY DEVICE AND REFRESH METHOD FOR THE SAME - A refresh method for a semiconductor memory device features high noise resistance, lower power consumption, and lower cost. All word lines of one or more memory cell blocks that have not been selected in a self refresh mode are controlled to have a floating potential substantially at ground level. Even when a word line and a bit line are short-circuited, this control prevents destruction of memory cell information, which may be caused by noise, and also prevents generation of leakage current. A fuse, etc., for preventing generation of leakage current is unnecessary, so that lower cost is realized. | 03-19-2009 |
