Patent application number | Description | Published |
20120078618 | METHOD AND APPARATUS FOR GENERATING LATTICE VECTOR QUANTIZER CODEBOOK - A method and an apparatus for generating a lattice vector quantizer codebook are disclosed. The method includes: storing an eigenvector set that includes amplitude vectors and/or length vectors, where the amplitude vectors and/or length vectors are different from each other and correspond to a root leader of a lattice vector quantizer; storing storage addresses of the amplitude vectors and length vectors, where the amplitude vectors and length vectors correspond to the root leader and are in the eigenvector set; and generating a lattice vector quantizer codebook according to the eigenvector set and the storage addresses. | 03-29-2012 |
20130304784 | SIGNAL PROCESSING METHOD AND DEVICE - A data processing method is disclosed, including: twiddling input data, so as to obtain twiddled data; pre-rotating the twiddled data by using a symmetric rotate factor, where the rotate factor is a·W | 11-14-2013 |
20150163587 | Audio Information Processing Method and Apparatus - An audio information processing method and apparatus are provided. The method includes determining a first camera, acquiring first audio information collected by the first audio collecting unit, acquiring second audio information collected by the second audio collecting unit, processing the first audio information and the second audio information to obtain third audio information, where for the third audio information, a gain of a sound signal coming from a shooting direction of the first camera is a first gain and a gain of a sound signal coming from an opposite direction of the shooting direction is a second gain, and outputting the third audio information. When the method or the apparatus of the present application is adopted, in synchronously output audio information, volume of a target sound source in a final video image is higher than volume of noise or an interfering sound source outside the video image. | 06-11-2015 |
Patent application number | Description | Published |
20100283926 | METHOD AND RESULTING CAPACITOR STRUCTURE FOR LIQUID CRYSTAL ON SILICON DISPLAY DEVICES - In a specific embodiment, the present invention provides an LCOS device. The device has a semiconductor substrate, e.g., silicon substrate. The device has a transistor formed within the semiconductor substrate. The transistor has a first node, a second node, and a row node. A first capacitor structure is coupled to the transistor. The first capacitor structure includes a first polysilicon layer coupled to the second node of the transistor. The first capacitor structure also has a first capacitor insulating layer overlying the first polysilicon layer and a second polysilicon layer overlying the insulating layer. The second polysilicon layer is coupled to a reference potential, e.g., ground. The device has a second capacitor structure coupled to the transistor. The second capacitor structure has a first metal layer coupled to the reference potential, a second capacitor insulating layer, and a second metal layer coupled to the second node of the transistor. A pixel electrode comprises the first metal layer. The pixel electrode is coupled to the second node of the transistor. A mirror surface is on the pixel electrode. The device has a light shielding layer formed from a portion of the second metal layer. | 11-11-2010 |
20140367753 | CMOS DEVICE WITH DOUBLE-SIDED TERMINALS AND METHOD OF MAKING THE SAME - A transistor device includes a semiconductor substrate having a first surface and a second surface opposite the first surface, a gate structure disposed on the first surface and configured to form a channel region, and source and drain regions disposed on opposite sides of the channel region. The device also includes a source terminal and a drain terminal disposed on the second surface. The source and drain terminals are connected to the respective source and drain regions. The transistor device further include a body terminal disposed. on the second. surface and configured to connect the highest or lowest voltage supply to the semiconductor substrate. | 12-18-2014 |
20150187794 | METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI - A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors. | 07-02-2015 |
20150214287 | INDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device and a method of manufacturing the semiconductor device are disclosed. The semiconductor device includes an inductor disposed on a surface of an intermetallic dielectric layer at a location below which no virtual interconnect members are present. Thus, parasitic capacitance is reduced or eliminated and the Q value of the inductor is high. | 07-30-2015 |