Patent application number | Description | Published |
20090055620 | DEFECT MANAGEMENT USING MUTABLE LOGICAL TO PHYSICAL ASSOCIATION - The application relates to defect management using mutable logical to physical association. Embodiments disclosed utilize mutable mapping between logical blocks and physical blocks. Dynamically updated mapping data, which mutably associates the logical blocks and the physical blocks, also includes physical block defect allocations. | 02-26-2009 |
20100315872 | Multilevel Cell Memory Devices Having Reference Point Cells - Embodiments of the disclosure include multilevel memory cell devices that utilize reference point cells to determine the states of other cells. Embodiments of the disclosure also include methods of storing data to and retrieving data from multilevel memory cell devices utilizing reference point cells. In one embodiment, a multilevel memory cell device includes user data cells, a reference point cell, and a controller. The user data cells each has one of a plurality of states. The reference point cell has a first state. The controller determines the states of the user data cells based at least in part on the first state of the reference point cell. | 12-16-2010 |
20110099321 | ENABLING SPANNING FOR A STORAGE DEVICE - A storage device, e.g., an SSD, is configured to enable spanning for a logical block between pages of the device. In one example, a device includes a data storage module to receive data to be stored, wherein the data comprises a plurality of logical blocks, and wherein a size of the plurality of logical blocks exceeds a size of a first page of the device, and a spanning determination module to determine whether to partition one of the plurality of logical blocks into a first partition and a second partition, wherein the data storage module is configured to partition the one of the plurality of logical blocks into the first partition and the second partition and to store the first partition in the first page and the second partition in a second, different page when the spanning determination module determines to partition the one of the plurality of logical blocks. | 04-28-2011 |
20110099350 | BLOCK BOUNDARY RESOLUTION FOR MISMATCHED LOGICAL AND PHYSICAL BLOCK SIZES - The present disclosure describes various techniques resolving block boundary issues and reconstructing logical blocks in a block access storage device when there are resulting mismatches between logical and physical block sizes or alignments, such that logical blocks span multiple physical block boundaries in irregular ways. In one example, a method comprises the following features: receiving logical block addresses that are associated with a sequence of logical blocks; and locating a first portion of a logical block within a first physical block that is stored in a block access storage device based upon a logical block address of the logical block, wherein the logical block is part of the sequence of logical blocks, and wherein at least two logical blocks within the sequence of logical blocks have different sizes. | 04-28-2011 |
20110138222 | DATA STORAGE DEVICES AND METHODS FOR POWER-ON INITIALIZATION - Methods and systems are disclosed to generate a data map for a data storage device. A data map may be generated by scanning, during a power-on initialization process, data units of data stored on a data storage medium of a data storage device. The scanning may start from a selected data unit and proceed through the data units in an order opposite to a write order to identify a first data unit that is not fully erased. Also. an error recovery status of the first data unit may be determined based on an error correction code. A likely erased status of the first data unit may be assigned when the determined error recovery status is unrecoverable. | 06-09-2011 |
20110141833 | LOW-WEAR WRITING IN A SOLID STATE MEMORY DEVICE - A method includes programming a non-volatile memory. The memory includes a plurality of cells, wherein each cell is configured to store a plurality of values, wherein each of value is represented by N digits where N is an integer greater than 1, wherein each of the plurality of cells is further configured to store electric charge representing a plurality of voltage levels, and wherein each of the plurality of voltage levels represents one of the plurality of values. Programming comprises providing the plurality of voltage levels into a first group of voltage levels and a second group of voltage levels in one of the plurality of cells, wherein a highest voltage level of the first group is less than or substantially equal to a lowest voltage level of the second group, and storing, in the first group of voltage levels, electric charge representing a value comprising, at most, N−1 digits. | 06-16-2011 |
20110188142 | DISC OPERATION SELECTION - A method of identifying a string or chain of efficient or “good enough” disc operations for processing (a pseudo optimal chain) is provided. A “pseudo optimal chain” comprises a string or chain of operations that, while not necessarily the optimal string or chain, provides an efficient sequence of operations that can be determined by comparing individual operations to predetermined selection criteria. In contrast to a true optimization technique that can require computing up to N! combinations for N operations, the string or chain of efficient or “good enough” disc operations allows for relatively simpler computations. | 08-04-2011 |
20110264843 | DATA SEGREGATION IN A STORAGE DEVICE - An example method includes providing at least two data storage areas in a memory, providing a first amount of over-provisioning for a first of the at least two data storage areas and a second amount of over-provisioning for a second of the at least two data storage areas, categorizing data based on a characteristic of the data, and storing the data in one of the at least two data storage areas based on the categorization. | 10-27-2011 |
20110283048 | STRUCTURED MAPPING SYSTEM FOR A MEMORY DEVICE - This disclosure is related to systems and methods for a structured mapping system for a memory device, such as a solid state data storage device. In one example, a data storage device may include a multi-level address mapping system. The multi-level address mapping system may be implemented completely independent of a host computer and a host computer operating system. Also, the multi-level mapping system may be stored to allow each level, or subsets of each level, to be re-written independently of the other levels or the other subsets. | 11-17-2011 |
20120191937 | GARBAGE COLLECTION MANAGEMENT IN MEMORIES - The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect. | 07-26-2012 |
20120260047 | GENERALIZED POSITIONAL ORDERING - Implementations described and claimed herein provide a method and system for managing execution of commands for a storage device, the method comprising determining a plurality of commands to be executed for the storage device and while a storage device is executing at least one command, determining an execution order for at least two of the plurality of commands. Alternate implementation described and claimed herein provide a computer readable memory for storing a data structure, the data structure comprising a cost table comprising a number of cells, each cell containing one or more cost values related to one of a plurality of traversals between two locations on a storage device wherein each of the plurality of traversals is related to completion of one of a plurality of commands and a benefit array comprising a number of cells, each cell containing a benefit value related to completion of one of the plurality of commands. | 10-11-2012 |
20120278564 | SECURE ERASURE OF DATA FROM A NON-VOLATILE MEMORY - Method and apparatus for securely erasing data from a non-volatile memory, such as but not limited to a flash memory array. In accordance with various embodiments, an extended data set to be sanitized from the memory is identified. The extended data set includes multiple copies of data having a common logical address and different physical addresses within the memory. The extended data set is sanitized in relation to a characterization of the data set. The data sanitizing operation results in the extended data set being purged from the memory and other previously stored data in the memory being retained. | 11-01-2012 |
20140379973 | GARBAGE COLLECTION MANAGEMENT IN MEMORIES - The disclosure is related to systems and methods of managing a memory. In a particular embodiment, a memory channel is disclosed that includes multiple memory units, with each memory unit comprising multiple garbage collection units. The memory channel also includes a controller that is communicatively coupled to the multiple memory units. The controller selects a memory unit of the multiple memory units for garbage collection based on a calculated number of memory units, of the multiple memory units, to garbage collect. | 12-25-2014 |