| Patent application number | Description | Published |
|---|
| 20080204294 | Analog-to-digital converter apparatus, systems, and methods - Various embodiments disclose apparatus, systems, and methods operating with a first circuit branch with transistors coupled in series between first and second supply nodes, and a second circuit branch with second transistors coupled in series between the first and second supply nodes. The second circuit branch may include a resistive unit coupled in series with the second transistors. The first and second circuit branches may receive analog information and to provide digital output information. The digital output information may include output values based on a relationship between a voltage across the first resistive unit and a voltage difference between first and second components of the analog input information. Other embodiments disclose additional apparatus, systems, and methods. | 08-28-2008 |
| 20090021623 | Systems, methods and devices for a CMOS imager having a pixel output clamp - Embodiments of a pixel read out circuit in an imager device is described. The pixel read out circuit includes an output node that is connected to a plurality of pixel cells. An output signal from a selected one of the plurality of pixel cells is applied to the output node. The pixel read out circuit also includes a clamp-out circuit that limits the magnitude of the output signal to a voltage determined by the voltage of a reference signal to prevent the output signal from reaching a level that might exceed the dynamic range of analog circuitry receiving the output signal. | 01-22-2009 |
| 20090090844 | BIASING APPARATUS, SYSTEMS, AND METHODS - Apparatus, methods, and systems for providing a uniform bias voltage in a biasing circuit to a plurality of pixels. The biasing circuit has a plurality of switches, including a first switch connected at a first end of a capacitor and a second end connected to a first ground. A second switch is connected at a first end to a bias voltage reference and at a second end to a gate of a biasing transistor and a second end of the capacitor. A third switch is connected at a first end to the first end of the capacitor and at a second end to the drain of the biasing transistor and a second ground. The first and the second switch are closed and the third switch is open to set a bias voltage on the capacitor. The first and second switch are open and the third switch is closed when the bias voltage is set on the capacitor. | 04-09-2009 |
| 20090108929 | Apparatuses and methods for providing offset compensation for operational amplifier - Apparatuses and methods for providing offset compensation include a primary amplifier which includes a first output, a second output, a first load input, and a second load input, a first feedback loop connected to the primary amplifier and which includes a first switch located between the first output of the primary amplifier and the first load input, and a first sampling capacitor coupled to the first switch between the first switch and the first load input and a second feedback loop connected to the primary amplifier and which includes a second switch located between the second output of the primary amplifier and the second load input, and a second sampling capacitor coupled to the second switch between the second switch and the second load input. | 04-30-2009 |
| 20090242738 | METHOD AND APPARATUS EMPLOYING DYNAMIC ELEMENT MATCHING FOR REDUCTION OF COLUMN-WISE FIXED PATTERN NOISE IN A SOLID STATE IMAGING SENSOR - An imager having a switching circuit that couples pixel columns to different sample and hold circuits to reduce the noticeability of column-wise fixed pattern noise. A controller randomly couples a pixel column to a sample and hold circuit, therefore fixed pattern noise emanating from a particular sample and hold circuit is not always associated with a single pixel column. Therefore the visual perception of fixed pattern noise associated with a particular sample and hold circuit is reduced. | 10-01-2009 |
| 20100123489 | PROCESS INSENSITIVE DELAY LINE - A delay line including a phase detector having two inputs and one output. The first input of the phase detector is connected to an input of the delay line. The second input of the phase detector is connected to an output of the delay line. The output of the phase detector is connected to a control circuit which controls current flow at a control node to produce a control voltage at the node. A voltage-controlled delay unit is responsible to the control voltage to control a delay applied to a signal at an input of the delay line. | 05-20-2010 |
