Patent application number | Description | Published |
20100258243 | METHOD OF MANUFACTURING LAMINATED BAMBOO SLIVER LUMBER - A method of manufacturing laminated bamboo sliver lumber, comprising steps of: selecting and using the bamboo outer slivers obtained from a bamboo and having an air dry density no less than about 0.95 g/cm | 10-14-2010 |
20110027529 | BAMBOO SCRIMBER AND MANUFACTURING METHOD THEREOF - A bamboo scrimber includes a plurality of pressure-pressed bamboo strips impregnated with an adhesive and modified through heat-treatment. Each of the bamboo strips is formed with a plurality of slots penetrating through the bamboo strip substantially in a direction of thickness defined by the bamboo strip. A substantially longitudinal direction defined by the slots is substantially consistent with a substantially longitudinal direction defined by fibers of the bamboo strip. | 02-03-2011 |
20140146902 | ANTENNA PATTERN MATCHING AND MOUNTING - A technique for improving wireless communication characteristics involving matching transmitter antenna patterns to receiver antenna patterns. In a specific implementation, the transmitter antenna pattern adapts to changing parameters, such as when a smartphone is initially held in a first orientation and is later held in a second orientation. Because the transmitter antenna pattern matches receiver antenna patterns, signal quality between stations improves. In some implementations, antennas are organized and mounted to maximize spatial diversity to cause peak gains in different directions. | 05-29-2014 |
20140153663 | ANTENNA PATTERN MATCHING AND MOUNTING - A technique for improving wireless communication characteristics involving matching transmitter antenna patterns to receiver antenna patterns. In a specific implementation, the transmitter antenna pattern adapts to changing parameters, such as when a smartphone is initially held in a first orientation and is later held in a second orientation. Because the transmitter antenna patterns match the receiver antenna patterns, signal quality between stations improves. In some implementations, antennas are organized and mounted to maximize spatial diversity to cause peak gains in different directions. | 06-05-2014 |
Patent application number | Description | Published |
20110022821 | System and Methods to Improve Efficiency of VLIW Processors - Exemplary embodiments provide microprocessors and methods to implement instruction packing techniques in a multiple-issue microprocessor. Exemplary instruction packing techniques implement instruction grouping vertically along packed groups of consecutive instructions, and horizontally along instruction slots of a multiple-issue microprocessor. In an exemplary embodiment, an instruction packing technique is implemented in a very long instruction word (VLIW) architecture designed to take advantage of instruction level parallelism (ILP). | 01-27-2011 |
20130086328 | General Purpose Digital Data Processor, Systems and Methods - The invention provides improved data processing apparatus, systems and methods that include one or more nodes, e.g., processor modules or otherwise, that include or are otherwise coupled to cache, physical or other memory (e.g., attached flash drives or other mounted storage devices) collectively, “system memory.” At least one of the nodes includes a cache memory system that stores data (and/or instructions) recently accessed (and/or expected to be accessed) by the respective node, along with tags specifying addresses and statuses (e.g., modified, reference count, etc.) for the respective data (and/or instructions). The tags facilitate translating system addresses to physical addresses, e.g., for purposes of moving data (and/or instructions) between system memory (and, specifically, for example, physical memory—such as attached drives or other mounted storage) and the cache memory system. | 04-04-2013 |
20160026574 | GENERAL PURPOSE DIGITAL DATA PROCESSOR, SYSTEMS AND METHODS - The invention provides improved data processing apparatus, systems and methods that include one or more nodes, e.g., processor modules or otherwise, that include or are otherwise coupled to cache, physical or other memory (e.g., attached flash drives or other mounted storage devices) collectively, “system memory.” At least one of the nodes includes a cache memory system that stores data (and/or instructions) recently accessed (and/or expected to be accessed) by the respective node, along with tags specifying addresses and statuses (e.g., modified, reference count, etc.) for the respective data (and/or instructions). The tags facilitate translating system addresses to physical addresses, e.g., for purposes of moving data (and/or instructions) between system memory (and, specifically, for example, physical memory-such as attached drives or other mounted storage) and the cache memory system. | 01-28-2016 |
Patent application number | Description | Published |
20100177851 | COMPENSATION METHOD, PROGRAM, RECORDING MEDIUM, AND RECEIVER FOR OFDM SIGNAL HAVING CFO AND DCO - A frequency offset (CFO) and a direct current component offset (DCO) occur in an OFDM scheme signal. To address this, such a method has been suggested which allows a pilot signal to be mixed with a communicated signal for compensation. However, if the pilot signal has a long duration, then a compensation method without the pilot signal is required to compensate signals during that period. However, no such a method is conventionally available which compensates for both the CFO and DCO without the pilot signal. Using the orthogonality of the OFDM signal, the matrix of a system in which CDO and DCO have occurred is subjected to the singular value decomposition, thereby predetermining the CFO candidate value which allows for demodulating zero from the received signal and an array of numerical values of CFO check data. Then, in a compensation section (17), the received signal is successively multiplied by the numerical values. The typical CFO value provided when the minimum value has been demodulated is outputted as an estimate value for compensation. | 07-15-2010 |
20100208783 | METHOD FOR CALCULATING CFO AND I/Q IMBALANCE COMPENSATION COEFFICIENTS, COMPENSATION METHOD USING THE SAME, AND METHOD FOR TRANSMITTING PILOT SIGNAL - The OFDM scheme based communication system is currently being put into practical use because of its effective use of frequencies and its enhanced resistance to multipath. However, since the OFDM scheme treats multiplexed signals with overlapped spectra, the orthogonality between carriers are corrupted and the error rate characteristic is degraded in the presence of CFO. Furthermore, since locally oscillated signals different by a phase of π/2 are difficult to obtain in demodulating the I/Q signal, an imbalance is caused between the I/Q signals, resulting in degradation in the error rate characteristic. The invention suggests a novel pilot signal, and a method for analytically determining compensation values for CFO and I/Q imbalance and compensating for those distortions using the resulting values. Furthermore, the invention is applicable not only to the OFDM scheme but also to any protocol that involves pilot signals. | 08-19-2010 |
20100246723 | METHOD FOR ESTIMATING AMOUNT OF DISTORTION IN CFO AND DCO, METHOD FOR COMPENSATING RECEIVED SIGNALS USING THE SAME, AND RECEIVER - A received signal delivered through a transmission line can be compensated for CFO and DCO to improve the SNR of the received signal, eventually resulting in an effective improvement in the error rate. In this context, methods for estimating and compensating for CFO and DCO have been studied, for example, using pilot signals or a blind method. However, the methods would require a huge amount of calculations for the estimation of CFO in the presence of DCO, as with the ML method, or never essentially eliminate errors from an estimated value. The received signal has convoluted influences through the transmission line, so that observation of the continual symbols of periodic pilot signals on the frequency axis shows just a phase shift by the CFO. Therefore, the CFO can be analytically found from the continual symbols of periodic pilot signals, thereby allowing the DCO to be estimated and both the CFO and the DCO to be compensated for. | 09-30-2010 |
20110206105 | METHOD FOR DETERMINING HYBRID DOMAIN COMPENSATION PARAMETERS FOR ANALOG LOSS IN OFDM COMMUNICATION SYSTEMS AND COMPENSATING FOR THE SAME - In a transmit/receive system, the carrier frequency offset (CFO), I/Q imbalance, and DC offset (DCO) can cause serious signal distortions. These analog losses can be compensated for individually or in combination of any two of them by following various methods that have been suggested. However, there have suggested no methods of simultaneously compensating, for these three types of losses that occur in actual devices at the same time. The present invention suggests a novel pilot signal that has a cyclic signal portion and a portion of two equally spaced continual signals. The invention provides a method for compensating for the CFO, I/Q imbalance, and DCO by simultaneously performing the time domain compensation and the channel estimation using those signal portions. The method also compensates for the I/Q imbalance and the channel response on the transmitter side in the OFDM scheme. | 08-25-2011 |
Patent application number | Description | Published |
20090153018 | PLASMA DISPLAY PANEL - Powder of a crystal body is disposed in positions respectively facing the discharge cells formed in the discharge space S defined between the front glass substrate and the back glass substrate of a PDP. The crystal body is included among an MgO crystal body having properties of causing CL (and PL) emission having a peak within a 200-nm to 300-nm wavelength range upon excitation by ultraviolet rays, and has properties of having a higher intensity of light emission caused by 146-nm wavelength ultraviolet light than the intensity of light emission caused by 172-nm wavelength ultraviolet light. | 06-18-2009 |
20100213818 | Plasma display panel and method of manufacturing same - A plasma display panel including a front substrate and a back substrate facing each other across a discharge space, and a plurality of row electrode pairs and a plurality of column electrodes extending in a direction orthogonal to the row electrodes. The row electrodes and said column electrodes being provided between the front substrate and the back substrate and forming unit light emission areas at intersections with each other within the discharge space. A crystal having a volumetric particle-size distribution in which a ratio of a crystal having a particle size of 0.7 μm or less is 25% or less, is provided in an area facing the discharge space between the front substrate and the back substrate. | 08-26-2010 |
20110309740 | Plasma display panel and method of manufacturing same - A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. | 12-22-2011 |
20110309741 | Plasma display panel and method of manufacturing same - A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. Among the magnesium oxide crystal particles there are magnesium oxide crystal particles having a particle diameter of at least 3500 angstroms. | 12-22-2011 |
20110309742 | Plasma display panel and method of manufacturing same - A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. The magnesium oxide crystal particles are arranged to be protruding closer to the discharge space than the surface of the metal oxide layer. | 12-22-2011 |
20110309743 | Plasma display panel and method of manufacturing same - A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. The magnesium oxide crystal particles are arranged on the discharge space side of the metal oxide layer, or alternatively, part of the magnesium oxide crystal particles are disposed within the metal oxide layer. | 12-22-2011 |
20120070616 | PLASMA DISPLAY PANEL AND METHOD OF MANUFACTURING SAME - A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. The magnesium oxide crystal particles are arranged to be protruding closer to the discharge space than the surface of the metal oxide layer. | 03-22-2012 |
20120306364 | PLASMA DISPLAY PANEL AND METHOD OF MANUFACTURING SAME - A plasma display panel includes a front substrate, a plurality of row electrode pairs arranged on the front substrate, a dielectric layer formed on the front substrate so as to cover the plurality of row electrodes, a metal oxide layer formed on the dielectric layer, a plurality of metal oxide crystal particles formed on the dielectric layer or on the metal oxide layer, a back substrate facing the front substrate to form a discharge space, a plurality of column electrodes arranged on the back substrate, and partition wall units formed on the plurality of column electrodes to partition the discharge space to form a plurality of discharge cells. | 12-06-2012 |
Patent application number | Description | Published |
20110169807 | PLASMA DISPLAY PANEL AND DRIVE METHOD THEREFOR - A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes. | 07-14-2011 |
20110169875 | PLASMA DISPLAY PANEL AND DRIVE METHOD THEREFOR - A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes. | 07-14-2011 |
20110169876 | PLASMA DISPLAY PANEL AND DRIVE METHOD THEREFOR - A plasma display panel and a drive method therefor, which can enhance a representation capability when displaying a dark image. The plasma display panel includes fluorophor layers containing magnesium oxide. The drive method includes a reset step to initialize all the pixel cells into states of one of a light-up mode and a light-off mode, and an address step in which the pixel cells are caused to perform address discharges selectively in accordance with pixel data, which are successively executed in each of a head subfield and a second subfield within a one-field display period. In reset step, a voltage that sets row electrodes on one side, in the row electrode pairs as an anode and sets the column electrodes set as a cathode is applied between the row electrodes on the one side and the column electrodes. | 07-14-2011 |