Patent application number | Description | Published |
20080277797 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 11-13-2008 |
20090091038 | AIR GAP FOR INTERCONNECT APPLICATION - The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer. | 04-09-2009 |
20100123224 | HIGH MECHANICAL STRENGTH ADDITIVES FOR POROUS ULTRA LOW-K MATERIAL - A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group. | 05-20-2010 |
20110115088 | INTERCONNECT WITH FLEXIBLE DIELECTRIC LAYER - An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion. | 05-19-2011 |
20120074535 | LOW DIELECTRIC CONSTANT MATERIAL - The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH | 03-29-2012 |
20130069234 | STRUCTURE AND METHOD FOR TUNABLE INTERCONNECT SCHEME - The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively. | 03-21-2013 |
20130216177 | METHOD OF FABRICATION POLYMER WAVEGUIDE - A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region. | 08-22-2013 |
20130223789 | OPTICAL BENCH ON SUBSTRATE - An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component. | 08-29-2013 |
20130228927 | INTERCONNECT STRUCTURES - A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure. | 09-05-2013 |
20140021611 | Novel Copper Etch Scheme for Copper Interconnect Structure - The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage. | 01-23-2014 |
20140091477 | SYSTEM AND METHOD FOR CHEMICAL-MECHANICAL PLANARIZATION OF A METAL LAYER - A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes depositing a low-k inter-metal layer over a semiconductor substrate, depositing a porogen-containing low-k layer over the low-k inter-metal layer, and etching a space for the via through the low-k inter-metal layer and the porogen-containing low-k layer. The method further includes depositing a metal layer, a portion of the metal layer filling the space for the via, another portion of the metal layer being over the porogen-containing low-layer, removing the portion of the metal layer over the porogen-containing layer by a CMP process, and curing the porogen-containing low-k layer to form a cured low-k layer. | 04-03-2014 |
20140203434 | Semiconductor Integrated Circuit and Fabricating the Same - A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a precursor. A decomposable polymer layer (DPL) is deposited between the conductive features of the precursor. The DPL is annealed to form an ordered periodic pattern of different types of polymer nanostructures. One type of polymer nanostructure is decomposed by a first selectively to form a trench. The trench is filled by a dielectric layer to form a dielectric block. The remaining types of polymer nanostructures are decomposed by a second selectively etching to form nano-air-gaps. | 07-24-2014 |
20140204466 | OPTICAL ELEMENT STRUCTURE AND OPTICAL ELEMENT FABRICATING PROCESS FOR THE SAME - An optical element structure and a fabricating process for the same are provided. The optical element fabricating process includes providing a substrate forming thereon a protrusion; and forming an over coating layer over the protrusion and the substrate by a deposition scheme to form an optical element. | 07-24-2014 |
20140212627 | SELF-ALIGNMENT DUE TO WETTABILITY DIFFERENCE OF AN INTERFACE - Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. | 07-31-2014 |
20140346675 | Semiconductor Integrated Circuit and Fabricating the Same - A semiconductor integrated circuit (IC) with a dielectric matrix is disclosed. The dielectric matrix is located between two conductive features. The matrix includes a first nano-scale dielectric block, a second nano-scale dielectric block, and a first nano-air-gap formed by a space between the first nano-scale dielectric block and the second nano-scale dielectric block. The matrix also includes third nano-scale dielectric block and a second nano-air-gap formed by a space between the second nano-scale dielectric block and the third nano-scale dielectric block. The nano-scale dielectric blocks share a first common width, and the nano-air-gaps share a second common width. An interconnect structure integrates the dielectric matrix with the conductive features. | 11-27-2014 |
20140355929 | WAVEGUIDE STRUCTURE AND METHOD FOR FABRICATING THE SAME - Embodiments of forming a waveguide structure are provided. The waveguide structure includes a substrate, and the substrate has an interconnection region and a waveguide region. The waveguide structure also includes a trench formed in the substrate, and the trench has a sloping sidewall surface and a substantially flat bottom. The waveguide structure further includes a bottom cladding layer formed on the substrate, and the bottom cladding layer extends from the interconnection region to the waveguide region, and the bottom cladding layer acts as an insulating layer in the interconnection region. The waveguide structure further includes a metal layer formed on the bottom cladding layer on the sloping sidewall surface. | 12-04-2014 |
20140376858 | Self-Alignment Due to Wettability Difference of an Interface - Some embodiments relate to a method of processing a workpiece. The workpiece includes a first surface region having a first wettability coefficient, and a second surface region having a second wettability coefficient that differs from the first wettability coefficient. A liquid, which corresponds to an optical structure, is dispensed on the first and second surface regions of the workpiece, wherein the liquid self-aligns to the second surface region due to the difference between the first and second wettability coefficients. The self-aligned liquid is hardened to form the optical structure. | 12-25-2014 |