Patent application number | Description | Published |
20110006428 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 01-13-2011 |
20110223762 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-15-2011 |
20120282768 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 11-08-2012 |
20120289062 | Liner Formation in 3DIC Structures - An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner. | 11-15-2012 |
20130249097 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 09-26-2013 |
20140084421 | Adhesion Promoter Apparatus and Method - A structure comprises a substrate having a plateau region and a trench region, a reflecting layer formed over a top surface of the trench region, a first adhesion promoter layer formed over the reflecting layer, a bottom cladding layer deposited over the first adhesion promoter layer, a core layer formed over the bottom cladding layer and a top cladding layer formed over the core layer. | 03-27-2014 |
20140167229 | PROTECTING LAYER IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure comprises a dielectric layer, a conduction piece, a first metal piece, a first protecting layer, and a second protecting layer. The conduction piece is surrounded by electrical materials of the dielectric layer. The first metal piece is over the dielectric layer and is in contact with the conduction piece. The first protecting layer covers dielectric materials of the dielectric layer that are not covered by the first metal piece. The second protecting layer is over the first protecting layer. | 06-19-2014 |
20140206110 | Etchant and Etching Process - A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. | 07-24-2014 |
20140206191 | Etchant and Etching Process - A system and method for manufacturing semiconductor devices is provided. An embodiment comprises using an etchant to remove a portion of a substrate to form an opening with a 45° angle with a major surface of the substrate. The etchant comprises a base, a surfactant, and an oxidant. The oxidant may be hydrogen peroxide. | 07-24-2014 |
20140231999 | Schemes for Forming Barrier Layers for Copper in Interconnect Structures - A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided. | 08-21-2014 |
20140252619 | INTERCONNECT STRUCTURE THAT AVOIDS INSULATING LAYER DAMAGE AND METHODS OF MAKING THE SAME - A method for forming an interconnect structure includes forming an insulating layer on a substrate. A damascene opening is formed through a thickness portion of the insulating layer. A diffusion barrier layer is formed to line the damascene opening. A conductive layer is formed overlying the diffusion barrier layer to fill the damascene opening. A carbon-containing metal oxide layer is formed on the conductive layer and the insulating layer. | 09-11-2014 |
20140252624 | Semiconductor Devices and Methods of Forming Same - A semiconductor device structure and methods of forming the same are disclosed. An embodiment is a method of forming a semiconductor device, the method comprising forming a first conductive line over a substrate, and conformally forming a first dielectric layer over a top surface and a sidewall of the first conductive line, the first dielectric layer having a first porosity percentage and a first carbon concentration. The method further comprises forming a second dielectric layer on the first dielectric layer, the second dielectric layer having a second porosity percentage and a second carbon concentration, the second porosity percentage being different from the first porosity percentage, and the second carbon concentration being less than the first carbon concentration. | 09-11-2014 |
20140269804 | Package Structure and Methods of Forming Same - A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer. | 09-18-2014 |
20140269805 | Light Coupling Device and Methods of Forming Same - An embodiment is a semiconductor device comprising an optical device over a first substrate, a vertical waveguide on a top surface of the optical device, the vertical waveguide having a first refractive index, and a capping layer over the vertical waveguide, the capping layer configured to be a lens for the vertical waveguide and the capping layer having a second refractive index. | 09-18-2014 |
20140363121 | Integrated Metal Grating - An integrated circuit includes a substrate, a metal grating disposed over the substrate, and a waveguide layer disposed over or under the metal grating. The metal grating is arranged to change a propagation direction of an optical signal and the waveguide layer is arranged to guide the optical signal to a desired direction. | 12-11-2014 |