Patent application number | Description | Published |
20080320216 | Translation Lookaside Buffer and Related Method and Program Product Utilized For Virtual Addresses - A program product, a translation lookaside buffer and a related method for operating the TLB is provided. The method comprises the steps of: a) when adding an entry for a virtual address to said TLB testing whether the attribute data of said virtual address is already stored in said CAM and if the attribute data is not stored already in said CAM, generating tag data for said virtual address such that said tag data is different from the tag data generated for the other virtual addresses currently stored in said RAM and associated to the new entry in said CAM for the attribute data, adding the generated tag data to said RAM and to the associated entry in said CAM, and setting a validity flag in said CAM for said associated entry; else if the attribute data is stored already in said CAM, adding the stored attribute data to the entry in said RAM for said virtual address; and when performing a TLB lookup operation: reading the validity flag and the tag data from the entry in said CAM, which is associated to the entry in said RAM for said virtual address, and simultaneously reading the absolute address and the tag data from the entry in said RAM for said virtual address, and generating a TLB hit only if the tag data read from said CAM is valid and matches the tag data read from said RAM. | 12-25-2008 |
20090217269 | SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR PROVIDING MULTIPLE QUIESCE STATE MACHINES - A system, method and computer program product for providing multiple quiesce state machines. The system includes a first controller including logic for processing a first quiesce request. The system also includes a second controller including logic for processing a second quiesce request. All or a portion of the processing of the second quiesce request overlaps in time with the processing of the first quiesce request. Thus, multiple quiesce requests may be active in the system at the same time. | 08-27-2009 |
20110320743 | MEMORY ORDERED STORE SYSTEM IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and computer implemented method for storing of data in the memory of a computer system in order at a fast rate is provided. The method includes launching a first store to memory. A wait counter is initiated. A second store to memory is speculatively launched when the wait counter expires. The second store to memory is cancelled when the second store achieves coherency prior to the first store to memory. | 12-29-2011 |
20130166803 | DEQUEUE OPERATION USING MASK VECTOR TO MANAGE INPUT/OUTPUT INTERRUPTIONS - A command is issued to reset one or more pending interrupt indicators and arbitrate for ownership of the interrupt. Responsive to a processor receiving the command, a check is made of a selected pending interrupt indicator. If the selected pending interrupt indicator is not set, another pending interrupt indicator is checked, instead of providing a negative response and reissuing the command. In this way, one dequeue command can replace multiple dequeue commands and the overhead of leaving and re-entering the interrupt handler is reduced. A negative response is reserved for those situations in which there are no pending interrupt indicators to be reset. | 06-27-2013 |
20140025922 | PROVIDING MULTIPLE QUIESCE STATE MACHINES IN A COMPUTING ENVIRONMENT - An aspect includes a method for operating on translation look-aside buffers (TLBs) in a multiprocessor environment including a plurality of logical partitions as zones. The method includes concurrently receiving a first quiesce request from a first processor of a first zone to quiesce processors of a first set of zones including the first zone and receiving a second quiesce request from a second processor of a second zone to quiesce processors of a second set of zones including the second zone. The second set of zones consists of separate zones from the first set of zones. Based on receiving the first quiesce request, only processors of the first set of zones are quiesced. Based on the processors of the first set of zones being quiesced, a first operation is performed on the TLBs. Based on the first operation being performed, the processors of the first set of zones are un-quiesced. | 01-23-2014 |
20140089607 | INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION - According to one aspect of the present disclosure, a method and technique for input/output traffic backpressure prediction is disclosed. The method includes: performing a plurality of memory transactions; determining, for each memory transaction, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determining a median value based on the determined traffic values; determining whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicating a prediction of a backpressure condition. | 03-27-2014 |
20140089621 | INPUT/OUTPUT TRAFFIC BACKPRESSURE PREDICTION - According to one aspect of the present disclosure a system and technique for input/output traffic backpressure prediction is disclosed. The system includes a processor unit and logic executable by the processor unit to: determine, for each of a plurality of memory transactions, a traffic value corresponding to a time for performing the respective memory transactions; responsive to determining the traffic value for a respective memory transaction, determine a median value based on the determined traffic values; determine whether successive median values are incrementing; and responsive to a quantity of successively incrementing median values exceeding a threshold, indicate a prediction of a backpressure condition. | 03-27-2014 |
20150149716 | WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES - A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time. | 05-28-2015 |
20150149727 | WRITE AND READ COLLISION AVOIDANCE IN SINGLE PORT MEMORY DEVICES - A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time. | 05-28-2015 |
20150154131 | DATA TRANSFER USING A DESCRIPTOR - A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit. | 06-04-2015 |
20150154139 | RESOURCE ALLOCATION BY VIRTUAL CHANNEL MANAGEMENT AND BUS MULTIPLEXING - According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable. | 06-04-2015 |
Patent application number | Description | Published |
20150049576 | HORIZONTAL AGITATOR - The invention relates to a horizontal agitator for producing a substantially horizontal flow in a wastewater treatment tank, a propeller being installed on a polygonal shaft driven by means of a submersible motor, wherein the propeller is produced form a first material, which is formed from a polymer reinforced with first fibres, and as hub has a sleeve which corresponds to the outer shape of the polygonal shaft and which is produced from a second material which is different from the first material. | 02-19-2015 |
20150063998 | HORIZONTAL AGITATOR - The invention relates to a horizontal agitator for producing a flow in a clarifier, a submersible motor and a propeller drivingly connected thereto forming an assembly unit, wherein a receiving portion for removably attaching the assembly unit is provided and can be supported on the bottom of the clarifier, and wherein a guide for guiding the assembly unit along a substantially vertical movement path between a surfacing position above a maximum nominal sewage level defined for the clarifier and the receiving portion is provided. In order to improve the efficiency of the horizontal agitator and to reduce complexity of manufacture, the guide is formed by at least one first cable extending between the surfacing position and the receiving portion. | 03-05-2015 |
20150290564 | ROTARY DISC FILTER DEVICE - A rotary disc filter device includes a rotor rotatable about an axis of rotation, having a plurality of disc-shaped filter members. Each disc-shaped filter member has two walls extending outwardly form the axis of rotation. At least one of the walls has the form of a frustum. | 10-15-2015 |
20150290565 | ROTARY DISC FILTER DEVICE - A rotary disc filter device includes a rotor rotatable about an axis of rotation. The rotor includes a plurality of disc-shaped filter members, each disc-shaped filter member having a frame. The frame is made of sheet metal elements which are connected with each other by rivets. | 10-15-2015 |