Patent application number | Description | Published |
20080225596 | HIGH ACCURACY ADAPTIVE PROGRAMMING - Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles. | 09-18-2008 |
20090040839 | READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION - Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memory cells, non-overlapped. System components can measure distributions rendered non-overlapped to uniquely identify states of such distributions. Identified state distributions can subsequently be disabled to render other state distributions non-overlapped, and therefore identifiable. In such a manner, read errors associated with overlapped bit states of multi-cell memory devices can be mitigated. | 02-12-2009 |
20090109721 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE. - An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines. | 04-30-2009 |
20090109758 | NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE - A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells. | 04-30-2009 |
20090109760 | DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES - Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell. | 04-30-2009 |
20090113115 | NON-VOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI-LEVEL CELLS WITHIN THE SAME MEMORY - A memory device is disclosed, and includes an array of memory cells and a partitioning system configured to address a first portion of the array in a single level cell mode, and a second portion of the array in a multi-level cell mode. | 04-30-2009 |
20090154234 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 06-18-2009 |
20090154260 | SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS - Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli | 06-18-2009 |
20090316481 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 12-24-2009 |
20100122146 | ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory. | 05-13-2010 |
20110080792 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 04-07-2011 |
20110122708 | METHOD AND APPARATUS FOR PERFORMING SEMICONDUCTOR MEMORY OPERATIONS - A semiconductor memory device and a method for performing a memory operation in the semiconductor memory device are provided. The semiconductor memory device includes a plurality of predetermined memory arrays, a bitline decoder, and a controller. The controller provides the memory operation signal to the bitline decoder and, after precharging bitlines of the plurality of predetermined memory arrays, performs the memory operation on selected memory cells in the one or more of the plurality of predetermined memory arrays in accordance with the memory operation signal. The bitline decoder includes a plurality of sector select transistors and determines selected ones of the plurality of predetermined memory arrays and selected rows and unselected rows within the selected ones of the plurality of predetermined memory arrays in response to the memory operation signal. The bitline decoder also precharges the bitlines of the plurality of predetermined memory arrays to a first voltage potential then shuts off the sector select transistors of unselected ones of the plurality of predetermined memory arrays and the unselected rows of the selected ones of the plurality of predetermined memory arrays while maintaining the sector select transistors of the selected rows of the selected ones of the plurality of predetermined memory arrays at the first voltage potential prior to the controller performing the memory operation. | 05-26-2011 |
20110149630 | HIGH READ SPEED ELECTRONIC MEMORY WITH SERIAL ARRAY TRANSISTORS - Providing a serial array semiconductor architecture achieving fast program, erase and read times is disclosed herein. By way of example, a memory architecture can comprise a serial array of semiconductors coupled to a metal bitline of an electronic memory device at one end of the array, and a gate of a pass transistor at an opposite end of the array. Furthermore, a second metal bitline is coupled to a drain of the pass transistor. A sensing circuit that measures current or voltage at the second metal bitline, which is modulated by a gate potential of the pass transistor, can determine a state of transistors of the serial array. Because of low capacitance of the pass transistor, the serial array can charge or discharge the gate of the pass transistor quickly, resulting in read times that are significantly reduced as compared with conventional serial semiconductor array devices. | 06-23-2011 |
20110305064 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 12-15-2011 |
20110305065 | NON-VOLATILE VARIABLE CAPACITIVE DEVICE INCLUDING RESISTIVE MEMORY CELL - A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device. | 12-15-2011 |
20110305066 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 12-15-2011 |
20110317466 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-29-2011 |
20120043520 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction. | 02-23-2012 |
20120074507 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 03-29-2012 |
20120087169 | CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR - A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation. | 04-12-2012 |
20120236650 | NAND ARCHTECTURE INCLUDING RESITIVE MEMORY CELLS - A non-volatile memory device includes a first select transistor, a second select transistor, and a first string of first memory cells provided between the first and second select transistors. Each first memory cell has a first resistive memory cell and a first transistor. The first resistive memory cell is in series with a gate of the first transistor. The non-volatile memory device further includes a first bit line coupled to a drain of the first select transistor and a plurality of word lines. Each word line is coupled to one of the first memory cells. | 09-20-2012 |
20120320660 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 12-20-2012 |
20120327701 | MEMORY ARRAY ARCHITECTURE WITH TWO-TERMINAL MEMORY CELLS - A non-volatile memory device includes a word line extending along a first direction; a bit line extending along a second direction; a memory unit having a read transistor coupled to the bit line, at least one two-terminal memory cell, and a select transistor, the two-terminal memory cell having a first end coupled to the word line and a second end coupled to a gate of the read transistor. The second end of the two-terminal memory cell is coupled to a common node shared by a drain of the select transistor and the gate of the read transistor. | 12-27-2012 |
20120327717 | HIGH READ SPEED MEMORY WITH GATE ISOLATION - Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture. | 12-27-2012 |
20130024742 | ERROR CORRECTION FOR FLASH MEMORY - Providing for single and multi-bit error correction of electronic memory is described herein. As an example, error correction can be accomplished by establishing a suspect region between bit level distributions of a set of analyzed memory cells. The suspect region can define potential error bits for the distributions. If a bit error is detected for the distributions, error correction can first be applied to the potential error bits in the suspect region. By identifying suspected error bits and limiting initial error correction to such identified bits, complexities involved in applying error correction to all bits of the distributions can be mitigated or avoided, improving efficiency of bit error corrections for electronic memory. | 01-24-2013 |
20130027079 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 01-31-2013 |
20130027081 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 01-31-2013 |
20130033923 | CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR - A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation. | 02-07-2013 |
20130148410 | NON-VOLATILE VARIABLE CAPACITIVE DEVICE INCLUDING RESISTIVE MEMORY CELL - A non-volatile variable capacitive device includes a capacitor defined over a substrate, the capacitor having an upper electrode and a resistive memory cell having a first electrode, a second electrode, and a switching layer provided between the first and second electrodes. The resistive memory cell is configured to be placed in a plurality of resistive states according to an electrical signal received. The upper electrode of the capacitive device is coupled to the second electrode of the resistive memory cell. The resistive memory cell is a two-terminal device. | 06-13-2013 |
20130194002 | RE-CONFIGURABLE MIXED-MODE INTEGRATED CIRCUIT ARCHITECTURE - An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells. | 08-01-2013 |
20130214241 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A method of forming a disturb-resistant non volatile memory device. The method includes providing a semiconductor substrate having a surface region and forming a first dielectric material overlying the surface region. A first wiring material overlies the first dielectric material, a doped polysilicon material overlies the first wiring material, and an amorphous silicon switching material overlies the said polysilicon material. The switching material is subjected to a first patterning and etching process to separating a first strip of switching material from a second strip of switching spatially oriented in a first direction. The first strip of switching material, the second strip of switching material, the contact material, and the first wiring material are subjected to a second patterning and etching process to form at least a first switching element from the first strip of switching material and at least a second switching element from the second strip of switching material, and a first wiring structure comprising at least the first wiring material and the contact material. The first wiring structure being is in a second direction at an angle to the first direction. | 08-22-2013 |
20130234092 | THREE DIMENSION PROGRAMMABLE RESISTIVE RANDOM ACCESSED MEMORY ARRAY WITH SHARED BITLINE AND METHOD - A method of forming a non-volatile memory device. A substrate is provided and a first dielectric material forms overlying the substrate. A first polysilicon material is deposited overlying the first dielectric material. A second dielectric material is deposited overlying the first polysilicon material. A second polysilicon material is deposited overlying the second dielectric material. A third dielectric material is formed overlying the second polysilicon material. The third dielectric material, the second polysilicon material, the second dielectric material, and the first polysilicon material is subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material, a third wordline and associated with a third switching device, and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and overlies the amorphous silicon material and connected to a common bitline. | 09-12-2013 |
20130295744 | INTERFACE CONTROL FOR IMPROVED SWITCHING IN RRAM - A memory device has a crossbar array including a first array of first electrodes extending along a first direction. A second array of second electrodes extends along a second direction. A non-crystalline silicon structure provided between the first electrode and the second electrode at an intersection defined by the first array and the second array. The non-crystalline silicon structure has a first layer having a first defect density and a second layer having a second defect density different from the first defect density. Each intersection of the first array and the second array defines a two-terminal memory cell. | 11-07-2013 |
20130308369 | SWITCHING DEVICE HAVING A NON-LINEAR ELEMENT - Method for a memory including a first, second, third and fourth cells include applying a read, program, or erase voltage, the first and second cells coupled to a first top interconnect, the third and fourth cells coupled to a second top interconnect, the first and third cells coupled to a first bottom interconnect, the second and fourth cells are to a second bottom interconnect, each cell includes a switching material overlying a non-linear element (NLE), the resistive switching material is associated with a first conductive threshold voltage, the NLE is associated with a lower, second conductive threshold voltage, comprising applying the read voltage between the first top and the first bottom electrode to switch the NLE of the first cell to conductive, while the NLEs of the second, third, and the fourth cells remain non-conductive, and detecting a read current across the first cell in response to the read voltage. | 11-21-2013 |
20140098619 | NON-VOLATILE MEMORY WITH OVERWRITE CAPABILITY AND LOW WRITE AMPLIFICATION - Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations. | 04-10-2014 |
20140133211 | RESISTIVE RANDOM ACCESS MEMORY EQUALIZATION AND SENSING - Providing for a two-terminal memory architecture that can mitigate sneak path current in conjunction with memory operations is described herein. By way of example, a voltage mimicking mechanism can be employed to dynamically drive un-selected bitlines of the memory architecture at a voltage observed by a selected bitline. According to these aspects, changes observed by the selected bitline can be applied to the un-selected bitlines as well. This can help reduce or avoid voltage differences between the selected bitline and the un-selected bitlines, thereby reducing or avoiding sneak path currents between respective bitlines of the memory architecture. Additionally, an input/output based configuration is provided to facilitate reduced sneak path current according to additional aspects of the subject disclosure. | 05-15-2014 |
20140146595 | CIRCUIT FOR CONCURRENT READ OPERATION AND METHOD THEREFOR - A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation. | 05-29-2014 |
20140146606 | PARALLEL BITLINE NONVOLATILE MEMORY EMPLOYING CHANNEL-BASED PROCESSING TECHNOLOGY - Providing for a new combination of non-volatile memory architecture and memory processing technology is described herein. By way of example, disclosed is a parallel bitline semiconductor architecture coupled with a channel-based processing technology. The channel based processing technology provides fast program/erase times, relatively high density and good scalability. Furthermore, the parallel bitline architecture enables very fast read times comparable with drain-based tunneling processes, achieving a combination of fast program, erase and read times far better than conventional non-volatile memories. | 05-29-2014 |
20140264226 | INTEGRATION OF AN AMORPHOUS SILICON RESISTIVE SWITCHING DEVICE - An integrated circuit device. The integrated circuit device includes a semiconductor substrate having a surface region. A gate dielectric layer overlies the surface region of the substrate. The device includes a MOS device having a p+ active region. The p+ active region forms a first electrode for a resistive switching device. The resistive switching device includes an amorphous silicon switching material overlying the p+ active region and a metal electrode overlies the first metal conductor structure. The metal electrode includes a metal material, upon application of a positive bias to the metal electrode, forms a metal region in the amorphous silicon switching material. The MOS device provides for a select transistor for the integrated circuit device. | 09-18-2014 |
20140264242 | DISTURB-RESISTANT NON-VOLATILE MEMORY DEVICE AND METHOD - A disturb-resistant nonvolatile memory device includes a substrate, a dielectric material overlying the semiconductor substrate, a first cell comprising a first wiring structure extending in a first direction overlying the dielectric material, a first contact region, a first resistive switching media, and a second wiring structure extending in a second direction orthogonal to the first direction, a second cell comprising the first wiring structure, a second contact region, a second resistive switching media, and a third wiring structure separated from the second wiring structure and parallel to the second wiring structure, and a dielectric material disposed at least in a region between the first switching region and the second switching region to electrically and physically isolate the first switching region and the second switching region. | 09-18-2014 |
20140268997 | PROGRAMMING TWO-TERMINAL MEMORY CELLS WITH REDUCED PROGRAM CURRENT - Providing for programming a two-terminal memory cell array with low sneak path current is described herein. Groups of two-terminal memory cells can be arranged into blocks or sub-blocks, along sets of bitlines and local wordlines. Further, groups of local wordlines within a given sub-block can be electrically isolated from bitlines outside the sub-block. A programming signal can be applied to the two-terminal memory cells from an associated local wordline thereof. Sneak path currents can be mitigated or avoided with respect to bitlines outside a particular sub-block, or on non-selected wordlines of the sub-block. This can significantly reduce a magnitude of combined sneak path current within the sub-block in response to the programming operation. | 09-18-2014 |
20140292368 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 10-02-2014 |
20140320166 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a V | 10-30-2014 |
20140327470 | FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY - A method for an FPGA includes coupling a first electrode of a first resistive element to a first input voltage, coupling a second electrode of a second resistive element to a second input voltage, applying a first programming voltage to a shared node of a second electrode of the first resistive element, a first electrode of the second resistive element, and to a gate of a transistor element, and changing a resistance state of the first resistive element to a low resistance state while maintaining a resistance state of the second resistive element, when a voltage difference between the first programming voltage at the second terminal and the first input voltage at the first terminal exceeds a programming voltage associated with the first resistive element. | 11-06-2014 |
20140328108 | WRITE AND ERASE SCHEME FOR RESISTIVE MEMORY DEVICE - A method for programming a two terminal resistive memory device, the method includes applying a bias voltage to a first electrode of a resistive memory cell of the device; measuring a current flowing through the cell; and stopping the applying of the bias voltage if the measured current is equal to or greater than a predetermined value. | 11-06-2014 |