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Hagishima
Daisuke Hagishima, Kawasaki-Shi JP
| Patent application number | Description | Published |
|---|---|---|
| 20100250223 | SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM - A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term. | 09-30-2010 |
Daisuke Hagishima, Kanagawa JP
| Patent application number | Description | Published |
|---|---|---|
| 20100224927 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A NAND-type nonvolatile semiconductor memory device which suppresses write error caused by hot carriers and has improved reliability is provided. On a main plane of a semiconductor substrate, a plurality of memory cell transistors connected in series with each other, and a select gate transistor connected to an end of the plurality of memory cell transistors are arranged. A first impurity layer of a conductivity type opposite to that of the substrate is formed as a common source/drain on the semiconductor substrate between the select gate transistor and the memory cell transistor connected thereto. An impurity concentration distribution of the first impurity layer is asymmetrical with respect to a first virtual plane being at equal distances from ends of the select gate electrode and the control gate electrode and being perpendicular to the main plane, and an impurity concentration of the first impurity layer on the memory cell transistor side is higher than that on the gate transistor side with reference to the first virtual plane. | 09-09-2010 |
Daisuke Hagishima, Tokyo JP
| Patent application number | Description | Published |
|---|---|---|
| 20090020803 | AGING DEVICE - An aging device according to an embodiment of the present invention includes a semiconductor substrate, first and second diffusion layers provided in a first element region, a floating gate provided above a channel region between the first and second diffusion layers, and a control gate electrode provided beside the floating gate with an interval in the lateral direction. A coupling capacitance between the floating gate and the control gate electrode is larger than a coupling capacitance between the floating gate and the semiconductor substrate. | 01-22-2009 |
| 20090186474 | Nonvolatile semiconductor storage device and manufacturing method therefor - A nonvolatile semiconductor storage device includes a semiconductor substrate; a plurality of isolation regions formed in the semiconductor substrate; an element-forming region formed between adjacent isolation regions; a first gate insulating film provided on the element-forming region; a floating gate electrode which is provided on the first gate insulating film and in which a width of a lower hem facing the element-forming region is narrower than a width of the element-forming region in a section taken in a direction perpendicular to a direction in which the isolation regions extend; a second gate insulating film provided on the floating gate electrode; and a control gate electrode provided on the second gate insulating film. | 07-23-2009 |