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Hag-Ju Cho

Hag-Ju Cho, Hwaseong-Si KR

Patent application number	Description	Published
20100164009	Method of manufacturing dual gate semiconductor device - The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.	07-01-2010
20100203716	METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DUAL GATE - A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.	08-12-2010

Hag-Ju Cho, Seoul KR

Patent application number	Description	Published
20090134453	Non-Volatile Memory Device with Improved Immunity to Erase Saturation and Method for Manufacturing Same - A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.	05-28-2009
20090184376	SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.	07-23-2009
20100193875	SEMICONDUCTOR DEVICE WITH DUAL GATES AND METHOD OF MANUFACTURING THE SAME - In a semiconductor device with dual gates and a method of manufacturing the same, a dielectric layer and first and second metallic conductive layers are successively formed on the semiconductor substrate having first and second regions. The second metallic conductive layer which is formed on the first metallic conductive layer of the second region is etched to form a metal pattern. The first metallic conductive layer is etched using the metal pattern as an etching mask. A polysilicon layer is formed on the dielectric layer and the metal pattern. The first gate electrode is formed by etching portions of the polysilicon layer, the metal pattern, and the first metallic conductive layer of the first region. The second gate electrode is formed by etching a portion of the polysilicon layer formed directly on the dielectric layer of the second region.	08-05-2010

Hag-Ju Cho, Gyeonggi-Do KR

Patent application number	Description	Published
20090253256	METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING TRANSISTORS WITH DIFFERENT GATE STRUCTURES - A semiconductor device has two transistors of different structure from each other. One of transistors is P-type and the other is N-type. One of the transistors includes a gate structure in which a polysilicon layer contacts a gate insulation film while the other transistor includes a gate structure in which a metal layer contacts a gate insulation film.	10-08-2009
20100124805	METHODS OF FORMING SEMICONDUCTOR DEVICES HAVING GATES WITH DIFFERENT WORK FUNCTIONS USING NITRIDATION - A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer	05-20-2010

Hag-Ju Cho, Hwansung-City KR

Patent application number	Description	Published
20090134466	DUAL WORK FUNCTION SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing dual work function devices starting from a single metal electrode and the device resulting therefrom are disclosed. In one aspect, the method includes a single-metal-single-dielectric (SMSD) CMOS integration scheme. A single dielectric stack comprising a gate dielectric layer and a dielectric capping layer and one metal layer overlying the dielectric stack are first deposited, forming a metal-dielectric interface. Upon forming the dielectric stack and the metal layer, at least part of the dielectric capping layer is selectively modified by adding work function tuning elements, the part being adjacent to the metal-dielectric interface.	05-28-2009