| Patent application number | Description | Published |
|---|
| 20090055970 | Yield increase in plants overexpressing the hsrp genes - A transgenic crop plant transformed by a Hookless-Like Stress-Related Polypeptide (HSRP) coding nucleic acid, wherein expression of the nucleic acid sequence in the crop plant results in the plant's increased root growth, and/or increased yield, and/or increased tolerance to environmental stress as compared to a wild type variety of the plant. Also provided are agricultural products, including seeds, produced by the transgenic crop plants. Also provided are isolated novel HSRPs and isolated novel nucleic acid coding HSRPs, and vectors and transgenic plant containing the same. | 02-26-2009 |
| 20100162434 | Yield Increase in Plants Overexpressing the SHSRP Genes - A transgenic crop plant transformed by a Serine Hydroxymethyltransferase-Like Stress-Related Polypeptide (SHSRP) coding nucleic acid, wherein expression of the nucleic acid sequence in the crop plant results in the plant's increased root growth, and/or increased yield, and/or increased tolerance to environmental stress as compared to a wild type variety of the plant Also provided are agricultural products, including seeds, produced by the transgenic crop plants. Also provided are isolated novel SHSRPs, and isolated novel nucleic acids encoding SHSRPs, and vectors and transgenic plant containing the same. | 06-24-2010 |
| 20110154531 | Yield Increase in Plants Overexpressing the MTP Genes - A transgenic crop plant transformed by a Membrane Transporter-like Polypeptide (MTP) coding nucleic acid, wherein expression of the nucleic acid sequence in the crop plant results in the plant's increased root growth, and/or increased yield, and/or increased tolerance to environmental stress as compared to a wild type variety of the plant. Also provided are agricultural products, including seeds, produced by the transgenic crop plants. | 06-23-2011 |
| Patent application number | Description | Published |
|---|
| 20080271014 | Lightweight World Switch - In one embodiment, a processor comprises one or more registers coupled to an execution core. The registers are configured to store an intercept configuration that identifies which of a plurality of intercept events are enabled for intercept during guest execution. Additionally, the intercept configuration identifies, for each enabled intercept event, which of at least two exit mechanisms are to be used in response to detection of the enabled intercept event. The execution core is configured to detect one of the enabled intercept events during execution of a guest and to exit the guest using the exit mechanism identified in the intercept configuration for that detected, enabled intercept event. | 10-30-2008 |
| 20090164758 | System and Method for Performing Locked Operations - A mechanism for performing locked operations in a processing unit. A dispatch unit may dispatch a plurality of instructions including a locked instruction and a plurality of non-locked instructions. One or more of the non-locked instructions may be dispatched before and after the locked instruction. An execution unit may execute the plurality of instructions including the non-locked and locked instruction. A retirement unit may retire the locked instruction after execution of the locked instruction. During retirement, the processing unit may begin enforcing a previously obtained exclusive ownership of a cache line accessed by the locked instruction. Furthermore, the processing unit may stall the retirement of the one or more non-locked instructions dispatched after the locked instruction until after the writeback operation for the locked instruction is completed. At some point in time after retirement of the locked instruction, the writeback unit may perform a writeback operation associated with the locked instruction. | 06-25-2009 |
| 20090187726 | Alternate Address Space to Permit Virtual Machine Monitor Access to Guest Virtual Address Space - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space. | 07-23-2009 |
| 20090187729 | Separate Page Table Base Address for Minivisor - In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specify the alternate address space for a data access, permitting the minivisor/VMM to read guest memory state via the alternate address space. In another embodiment, a processor may implement a page table base address register dedicated for the minivisor's use. In still another embodiment, the minivisor may be implemented as a specified entry point in the VMM address space. | 07-23-2009 |
| 20090276573 | Transient Transactional Cache - In one embodiment, a processor comprises an execution core, a level 1 (L1) data cache coupled to the execution core and configured to store data, and a transient/transactional cache (TTC) coupled to the execution core. The execution core is configured to generate memory read and write operations responsive to instruction execution, and to generate transactional read and write operations responsive to executing transactional instructions. The L1 data cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache. The TTC is also configured to cache transaction data accessed responsive to transactional read and write operations to track transactions. Each entry in the TTC is usable for transaction data and for transient data. | 11-05-2009 |
