Patent application number | Description | Published |
20090116306 | DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE - A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals. | 05-07-2009 |
20090147883 | DATA TRANSMITTER - Data transmitter includes a first and second output nodes terminated to a first level, a controller configured to generate an off signal that is activated by logically combining first and second data during a low-power mode, a first driver configured to drive the first or second output node to a second level in response to the first data and a second driver configured to drive the first or second output node to the second level with a driving force different from that of the first driver in response to the second data, the second driver being turned off when the off signal is activated. | 06-11-2009 |
20090243667 | OUTPUT DRIVING DEVICE - An output driving device capable of improving a slew rate is provided. The output driving device includes a push-pull type driving unit configured with a pull-up PMOS transistor and a pull-down NMOS transistor, wherein body biases of the pull-up PMOS transistor and the pull-down NMOS transistor are controlled for control of a slew rate of an output signal of the driving unit. | 10-01-2009 |
20090267579 | VOLTAGE REGULATOR - A voltage regulator with an adaptive bandwidth, including a first buffer chain, a voltage generating unit, a trimming capacitor unit, a second buffer chain, and a control unit. The first buffer chain delays a clock signal using an external voltage as a supply voltage. The voltage generating unit generates a regulated voltage on the basis a reference voltage. The trimming capacitor unit controls a load capacitance of the voltage generating unit. The second buffer chain delays the clock signal using the regulated voltage as a supply voltage. The control unit adjusts the load capacitance by detecting a delay difference of clocks output from the first and second buffer chains. | 10-29-2009 |
20090273995 | APPARATUS FOR REMOVING CROSSTALK IN SEMICONDUCTOR MEMORY DEVICE - An apparatus for removing crosstalk in a semiconductor memory device includes pads for receiving externally provided signals, transmission lines for delivering the signals received by each of the pads to corresponding elements in the apparatus, and capacitors, coupled between adjacent ones of the lines, for adjusting the transmission delay of the signals depending on a signal transmission mode between the adjacent lines. | 11-05-2009 |
20090302965 | SEMICONDUCTOR DEVICE - A semiconductor device includes transmission lines for conveying signals and transition detectors, each of which checks whether a transmission signal on each of the plurality of transmission lines is transited. If the signal is transited, its transition shape is detected. A signal mode determining unit determines signal transmission modes between adjacent transmission lines in response to output signals from the plurality of transition detectors. Delay units are coupled to the respective transmission lines for adjusting transmission delays of the transmission signals depending on corresponding output signal from the signal mode determining units. | 12-10-2009 |
20100034033 | RECEIVER OF SEMICONDUCTOR MEMORY APPARATUS - A receiver of a semiconductor memory apparatus includes a first input transistor configured to be turned ON when an input signal is equal to or more than a predetermined level; a second input transistor configured to be turned ON when the input signal is equal to or less than the predetermined level; a first output node voltage control unit configured to increase a voltage level of an output node when the first input transistor is turned ON; a second output node voltage control unit configured to decrease the voltage level of the output node when the second input transistor is turned ON; a third input transistor configured to increase the voltage level of the output node when an inversion signal of the input signal is equal to or less than the predetermined voltage level; and a fourth input transistor configured to decrease the voltage level of the output node when the inversion signal of the input signal is equal to or more than the predetermined voltage level. | 02-11-2010 |
20100039140 | BUFFER CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A buffer circuit of a semiconductor memory apparatus includes a buffering section configured to increase or decrease a voltage level of an output node by comparing a voltage level of an input signal with a voltage level of a reference voltage. A voltage compensation section applies a voltage to the output node in proportion to a variation of the reference voltage when the level of the reference voltage is lower than a target level. | 02-18-2010 |
20100039142 | INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. | 02-18-2010 |
20100044872 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 02-25-2010 |
20100117696 | DLL CIRCUIT, UPDATE CONTROL APPARATUS IN DLL CIRCUIT AND UPDATE METHOD OF DLL CIRCUIT - A delay locked loop (DLL) circuit includes a phase detection unit configured to generate a phase detection signal by comparing a phase of a reference clock signal with a phase of a feedback clock signal. An update control apparatus is configured to generate a valid interval signal and an update control signal by determining a difference between the number of first logical values and the number of second logical values of the phase detection signal in response to the reference clock signal. A shift register configured to update a delay value granted to a delay line in response to the update control signal when the valid interval signal is enabled. | 05-13-2010 |
20100148833 | DOMAIN CROSSING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS - The domain crossing circuit of a semiconductor memory apparatus for improving a timing margin includes a sampler that provides a sampling internal signal generated by delaying an internal input signal by a predetermined time in response to a clock and an edge information signal that defines an output timing of the sampling internal signal and an output stage that allows the sampling internal signal to be synchronized with the clock in response to the edge information signal to be output as a final output signal. | 06-17-2010 |
20100164568 | LOW POWER VARIABLE DELAY CIRCUIT - A variable delay circuit includes at least a fixed delay unit, a first selection unit, and variable delay unit. The fixed delay unit receives an input signal and a first delay selection signal indicative of a first delay, and outputs a first delayed signal that is substantially the input signal delayed by the first delay. The first selection unit receives the input signal, the first delayed signal, and a second delay selection signal, and outputs either the input signal or the first delayed signal based on the second delay selection signal to the variable delay unit. The variable delay unit also receives a third delay selection signal indicative of a third delay, and outputs a output signal that is substantially the output signal of the selection unit delayed by a third delay. The first delay is 0 or X multiples of M delay units. The third delay is a delay selected from 0 to N delay units. | 07-01-2010 |
20100164571 | PHASE MIXER AND DELAY LOCKED LOOP INCLUDING THE SAME - A phase mixer includes a phase mixing unit configured to mix a phase of a first input signal and a phase of a second input signal in response to a phase control signal and output a phase mixed signal whose phase is varied by one or more units of a unit phase value, and a phase value adjusting unit configured to control an operation of the phrase mixing unit so that the unit phase value is adjusted in response to a code signal coding at least one of a process, voltage, or temperature (PVT) variation. | 07-01-2010 |
20100250994 | DATA PATTERN DETECTING CIRCUIT AND OUTPUT DRIVER INCLUDING THE SAME - Disclosed is an output driver capable of solving problems that occur when outputting the same data successively by using a data pattern detecting circuit. The data pattern detecting circuit includes a first data storage unit configured to receive data of a first line and store the received data until a next data is inputted through the first line, a second data storage unit configured to receive data of a second line and store the received data until a next data is inputted through the second line, and a detection signal output unit configured to activate a pattern detection signal when data stored in the first data storage unit and data stored in the second data storage unit have the same logic level. | 09-30-2010 |
20100301912 | DELAY LOCKED LOOP AND DELAY LOCKING METHOD HAVING BURST TRACKING SCHEME - A Delay Locked Loop (DLL) includes a replica delay unit configured to delay an output clock to generate a feedback clock; a phase detector configured to measure a phase difference between the feedback clock and an input clock; a quantization unit configured to quantize the phase difference measured by the phase detector; and a delay unit configured to delay the input clock based on a quantization result from the quantization unit to generate the output clock. | 12-02-2010 |
20100309732 | DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group. | 12-09-2010 |
20100315139 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is able to generate an output enable signal in response to a read command and CAS latency information. The semiconductor memory device includes a delay locked loop configured to detect a phase difference of an external clock signal and a feedback clock signal, generate a delay control signal corresponding to the detected phase difference, and generate a DLL clock signal by delaying the external clock signal for a time corresponding to the delay control signal, a delay configured to output an active signal as an output enable reset signal in response to the delay control signal and an output enable signal generator configured to be reset in response to the output enable reset signal and generate an output enable signal in response to a read signal and a CAS latency signal by counting the external clock signal and the DLL clock signal. | 12-16-2010 |
20110001533 | SAMPLING CIRCUIT - A sampling circuit for use in a semiconductor device, includes a first sampling unit configured to sample a data signal in synchronism with a reference clock signal and output a first output signal, a second sampling unit configured to sample a delayed data signal in synchronism with the reference clock signal and output a second output signal, and an output unit configured to combine the first and second output signals and output a sampling data signal. | 01-06-2011 |
20110058433 | LATENCY CONTROL CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR CONTROLLING LATENCY - A latency control circuit includes a path calculator configured to calculate a delay value of a path that an input signal is to go through inside a chip and output the delay value as path information, a delay value calculator configured to output delay information representing a delay value for delaying the input signal based on a latency value of the input signal and the path information, and a delayer configured to delay the input signal by a delay corresponding to the delay information. | 03-10-2011 |
20110156772 | INTERFACE APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND INTERFACING METHOD THEREOF - An interface apparatus for a semiconductor integrated circuit and an interfacing method thereof controls the VOX of differential signals to a target level in response to the differential signals being outputted by an output block. The interface apparatus for a semiconductor integrated circuit includes an output block configured to output differential signals output by an internal circuit a detector configured to detect a timing error of the differential signals; and a controller configured to control a timing of the differential signals output by the internal circuit according to a detection result of the detector. | 06-30-2011 |
20110267117 | DATA INPUT/OUTPUT APPARATUS AND METHOD FOR SEMICONDUCTOR SYSTEM - A semiconductor memory device includes: a strobe signal reception unit configured to receive a strobe signal and generate a tracking clock signal; a clock reception unit configured to receive a clock signal and generate an internal clock signal; a plurality of data reception units configured to receive parallel data in accordance with the internal clock signal and generate internal data; and a phase control unit configured to control the phase of the internal clock signal to track the tracking clock signal and to compensate for a variation in the phase of the internal clock signal while the data is received. | 11-03-2011 |
20110309867 | PHASE LOCKED LOOP - A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal. | 12-22-2011 |
20120105119 | INTEGRATED CIRCUIT - An integrated circuit includes a delay locked loop configured to delay a reference clock signal by a delay time for delay locking and generate a delay locked clock signal, a clock transmission circuit configured to transmit the delay locked clock signal in response to a clock transmission signal, a duty correction circuit configured to perform duty correction operation on an output clock signal of the clock transmission circuit, and a clock transmission signal generation circuit configured to generate the clock transmission signal in response to a command and burst length information. | 05-03-2012 |
20120112824 | FILTER CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME - A filter circuit includes a plurality of shifting units configured to each store an initial value, receive at least one input signal, and shift the stored value to a next shifting unit in sequence from among the shifting units in response to at least one input signal, and an initial value setting unit configured to set the initial stored values of the shifting units to different sets of initial stored values in response to different filter setting signals, respectively, wherein the different filter setting signals represent respectively different criteria for filtering the at least one input signal, wherein the initially stored values have a first logic value or a second logic value, wherein the filter circuit is configured to activate an output signal when the first logic value is shifted to a selected shifting unit among the plurality of shifting units. | 05-10-2012 |
20120161859 | INTERNAL SUPPLY VOLTAGE GENERATING CIRCUIT AND METHOD FOR GENERATING INTERNAL SUPPLY VOLTAGE - An internal supply voltage generating circuit includes a clock comparator configured to compare a first clock signal having clock information corresponding to a level of a reference voltage with a second clock signal having clock information corresponding to a level of an internal supply voltage, a control signal generator configured to generate a driving control voltage having a voltage level corresponding to an output signal of the clock comparator, and a driver configured to drive a terminal of the internal supply voltage in response to the driving control voltage. | 06-28-2012 |
20120194239 | DELAY LOCKED LOOP - A DLL circuit includes a common delay line configured to generate a delay locked clock by selectively delaying a source clock by one or more unit delays in response to a first delay control code or a second delay control code, a clock cycle detector configured to compare a phase of the source clock with a phase of the delay locked clock in a cycle detection mode and generate the first delay control code corresponding to a delay amount of a cycle of the source clock based on a result of comparing the phases of the source and delay locked clocks, a feedback delay configured to delay the delay locked clock and output a feedback clock, and a delay amount controller configured to compare the phase of the source clock with a phase of the feedback clock in a delay locking mode and change the second delay control code based on a result of comparing the source and feedback clocks. | 08-02-2012 |
20120268180 | DELAY LOCKED LOOP - A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated. | 10-25-2012 |
20130033294 | COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME - A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result. | 02-07-2013 |
20130076401 | INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS - The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal. | 03-28-2013 |
20130099838 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL. | 04-25-2013 |
20130113518 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 05-09-2013 |
20130222025 | PHASE LOCKED LOOP - A phase locked loop includes a phase detector configured to compare a phase of an input clock with a phase of a feedback clock to produce a phase comparison result, an initial frequency value provider configured to detect a frequency of the input clock and provide a frequency detection result, a controller configured to generate a frequency control signal based on the phase comparison result and the frequency detection result, and an oscillator configured to generate an output clock in response to the frequency control signal. | 08-29-2013 |
20130249593 | MAJORITY DECISION CIRCUIT - A majority decision circuit includes: a majority decision unit configured to compare first data with second data to decide whether one of the first data and the second data has more bits with a first logical value; and an offset application unit configured to control the majority decision unit so that the majority decision unit decides, in a case when the number of bits with the first logical value among the first data is equal to the number of bits with the first logical value among the second data, that the first data have more bits with the first logical value if offset is a first setting value in a first phase and decides that the second data have more bits with the first logical value if the offset is a second setting value in a second phase. | 09-26-2013 |
20130294186 | PHASE-LOCKED LOOP AND INTEGRATED CIRCUIT CHIP INCLUDING THE SAME, AND TEST SYSTEM INCLUDING THE INTEGRATED CIRCUIT CHIP - A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock. | 11-07-2013 |
20140068112 | SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF - A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal. | 03-06-2014 |
20140103981 | COUNTING CIRCUIT OF SEMICONDUCTOR DEVICE AND DUTY CORRECTION CIRCUIT OF SEMICONDUCTOR DEVICE USING THE SAME - A counting circuit of a semiconductor device includes a plurality of counting units configured to count respective bits of counting codes in response to a plurality of counting clocks, respectively, and to control in a counting direction in response to a counting control signal; a clock toggling control unit configured to control the number of counting clocks that toggle among the plurality of counting clocks in response to clock control signals; and a counting operation control unit configured to compare a value of target codes and a value of the counting codes, and to determine a value of the counting control signal according to a comparison result. | 04-17-2014 |
20140184294 | DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF - A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal. | 07-03-2014 |
20150042387 | DATA RECOVERY CIRCUIT AND OPERATING METHOD THEREOF - A data recovery circuit may include a data sampling unit suitable for sampling source data including an edge data using data clocks and an edge clock, a data extraction unit suitable for extracting the edge data from sampled data outputted from the data sampling unit, a control signal generation unit suitable for generating a phase control signal in response to the edge data, and a multi-clock control unit suitable for controlling phases of the data clocks and the edge clock in response to the phase control signal. | 02-12-2015 |
20150076614 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 03-19-2015 |
20150076703 | SEMICONDUCTOR MEMORY DEVICE HAVING PADS - A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power. | 03-19-2015 |