Patent application number | Description | Published |
20100296338 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 11-25-2010 |
20100314598 | PHASE CHANGE MEMORY DEVICE HAVING BIT-LINE DISCHARGE BLOCK AND METHOD OF FABRICATING THE SAME - A phase change memory device capable of fully discharging bit lines, even while occupying a relatively small area, and a fabricating method thereof are presented. The phase change memory device includes a semiconductor substrate, a word line area, a discharge line area, a switching PN diode, a dummy PN diode, a phase change structure, and a bit line. The word line area is formed in a memory cell area of the semiconductor substrate. The discharge line area is formed in the bit-line discharge area of the semiconductor substrate. The switching PN diode is formed on the word line area. The dummy PN diode is formed on the discharge line area. The phase change structure is formed on the switching PN diode and is electrically connected to the switching diode. The bit line is electrically connected to the phase change structure and the dummy PN diode. | 12-16-2010 |
20100315866 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 12-16-2010 |
20100327251 | PHASE CHANGE MEMORY DEVICE HAVING PARTIALLY CONFINED HEATING ELECTRODES CAPABLE OF REDUCING HEATING DISTURBANCES BETWEEN ADJACENT MEMORY CELLS - A phase change memory device having partially confined heating electrodes capable of reducing thermal disturbances between adjacent memory cells is presented. The phase change memory device includes a plurality of active regions, a plurality of switching elements, a plurality of heating electrodes, and a plurality of phase change structure lines. The active regions being linear and parallel to each other. The switching elements are coupled to the active regions. The heating electrodes are on and coupled to the switching elements. The phase change structure lines are coupled to the heating electrodes such that the phase change structure lines are substantially vertical to the active regions. The phase change structure lines includes a plurality of plugs projecting downwards that couple to overlapped portions of the heating electrodes. | 12-30-2010 |
20110073829 | PHASE CHANGE MEMORY DEVICE HAVING A HEATER WITH A TEMPERATURE DEPENDENT RESISTIVITY, METHOD OF MANUFACTURING THE SAME, AND CIRCUIT OF THE SAME - A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity. | 03-31-2011 |
20110075473 | CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME - A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier. | 03-31-2011 |
20110143477 | METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE - A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns. | 06-16-2011 |
20130037874 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 02-14-2013 |
20130039123 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 02-14-2013 |
20130043456 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-in change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 02-21-2013 |
20130094285 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 04-18-2013 |
20130146831 | PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES - A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer, | 06-13-2013 |
20140166965 | RESISTIVE MEMORY DEVICE AND FABRICATION METHOD THEREOF - A resistive memory device may include a bottom structure, a memory cell structure disposed on the bottom structure, and a data storage material disposed to surround an outer sidewall of the memory cell structure. | 06-19-2014 |
20140169065 | HIGH VOLTAGE GENERATING CIRCUIT FOR RESISTIVE MEMORY APPARATUS - A high voltage generating circuit for a resistive memory apparatus is provided. The high voltage generating circuit includes a capacitor spaced from a semiconductor substrate and electrically insulated from the semiconductor substrate. A switching device, which is electrically connected to the capacitor, is electrically insulated from the semiconductor substrate. | 06-19-2014 |
20140209847 | PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES - A phase-change memory device with an improved current characteristic is provided. The phase-change memory device includes a metal word line, a semiconductor layer of a first conductivity type being in contact with the metal word line, and an auxiliary diode layer being in contact with metal word line and the semiconductor layer. | 07-31-2014 |
20140286089 | SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area. | 09-25-2014 |
20140286090 | SEMICONDUCTOR INTEGRATED CIRCUIT SYSTEM AND METHOD FOR DRIVING THE SAME - A semiconductor integrated circuit system includes a phase-change line including a first phase-change area constituting a first memory cell and a second phase-change area constituting a second memory cell, a write current providing unit configured to phase-change a selected one of the first and second phase-change areas, and a phase-change compensation unit configured to restore the other of the first and second phase-change areas by compensating for a dummy phase-change caused in the other phase-change area due to a phase-change of the selected phase-change area. | 09-25-2014 |
20140301137 | PHASE-CHANGE MEMORY DEVICE HAVING PHASE-CHANGE REGION DIVIDED INTO MULTI LAYERS AND OPERATING METHOD THEREOF - A phase-change memory device including a multi-level cell and an operation method thereof are provided. The device includes a first phase-change material layer to which a current is provided from a heating electrode, and a second phase-change material layer formed with continuity to the first phase-change material layer and having a different width from the first phase-change material layer, and to which a current is provided from the heating electrode. The second phase-change material layer includes a material having smaller resistivity and a lower crystallization rate than the first phase-change material layer. | 10-09-2014 |
20140325120 | RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF - A resistive memory device includes a memory cell array including a unit memory cell coupled between a word line and a bit line, wherein the unit memory cell includes a data storage material and a non-silicon-substrate-based type bidirectional access device coupled in series, a path setting circuit coupled between the bit line and the word line, suitable for providing a program pulse toward the bit line or the word line based on a path control signal, a forward write command, and a reverse write command, and a control unit suitable for providing a write path control signal, a forward program command, and a reverse program command based on an external command signal. | 10-30-2014 |