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| 20100296338 | NONVOLATILE MEMORY CELL, NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A nonvolatile memory cell is able to reduce the size per the unit area by employing a dual gate structure where the chalcogenide compound is used for a channel. The nonvolatile memory cell includes a phase-change layer, a first and a second gate that are in contact with sides of the phase-change layer to face each other across the phase-change layer and control a current flowing through the phase-change layer by each gate being arranged to induce the phase transition of the phase-change layer independently of the other. | 11-25-2010 |
| 20100314598 | PHASE CHANGE MEMORY DEVICE HAVING BIT-LINE DISCHARGE BLOCK AND METHOD OF FABRICATING THE SAME - A phase change memory device capable of fully discharging bit lines, even while occupying a relatively small area, and a fabricating method thereof are presented. The phase change memory device includes a semiconductor substrate, a word line area, a discharge line area, a switching PN diode, a dummy PN diode, a phase change structure, and a bit line. The word line area is formed in a memory cell area of the semiconductor substrate. The discharge line area is formed in the bit-line discharge area of the semiconductor substrate. The switching PN diode is formed on the word line area. The dummy PN diode is formed on the discharge line area. The phase change structure is formed on the switching PN diode and is electrically connected to the switching diode. The bit line is electrically connected to the phase change structure and the dummy PN diode. | 12-16-2010 |
| 20100315866 | PHASE CHANGE MEMORY DEVICE HAVING MULTI-LEVEL AND METHOD OF DRIVING THE SAME - A phase change memory device having a multi-level and a method of driving the same are presented. The disclosed phase change memory device includes variable resistors and shifting units. The variable resistors are interchanged into set and reset states in response to an applied current. The shifting units, which are connected to the variable resistors, shift resistance distribution in the set and reset state of the variable resistors by a predetermined level. | 12-16-2010 |
| 20100327251 | PHASE CHANGE MEMORY DEVICE HAVING PARTIALLY CONFINED HEATING ELECTRODES CAPABLE OF REDUCING HEATING DISTURBANCES BETWEEN ADJACENT MEMORY CELLS - A phase change memory device having partially confined heating electrodes capable of reducing thermal disturbances between adjacent memory cells is presented. The phase change memory device includes a plurality of active regions, a plurality of switching elements, a plurality of heating electrodes, and a plurality of phase change structure lines. The active regions being linear and parallel to each other. The switching elements are coupled to the active regions. The heating electrodes are on and coupled to the switching elements. The phase change structure lines are coupled to the heating electrodes such that the phase change structure lines are substantially vertical to the active regions. The phase change structure lines includes a plurality of plugs projecting downwards that couple to overlapped portions of the heating electrodes. | 12-30-2010 |
| 20110073829 | PHASE CHANGE MEMORY DEVICE HAVING A HEATER WITH A TEMPERATURE DEPENDENT RESISTIVITY, METHOD OF MANUFACTURING THE SAME, AND CIRCUIT OF THE SAME - A phase change memory device having a heater that exhibits a temperature dependent resistivity which provides a way of reducing a reset current is presented. The phase change memory device includes a phase change pattern and a heating electrode contacted with the phase change pattern. The heating electrode includes a smart heating electrode such that the smart heating layer is formed of a conduction material that exhibits an increase in resistance as a function of an increase in temperature, i.e., a positive temperature dependent resistivity. | 03-31-2011 |
| 20110075473 | CIRCUIT AND METHOD FOR GENERATING REFERENCE VOLTAGE, PHASE CHANGE RANDOM ACCESS MEMORY APPARATUS AND READ METHOD USING THE SAME - A circuit for generating a reference voltage includes at least one reference cell, a reference cell write driver, a reference cell sense amplifier, and a voltage compensation unit. The reference cell is a variable resistance memory cell. The reference cell write driver writes data to the reference cell. The reference cell sense amplifier reads out the data stored in the reference cell on the basis of a predetermined reference voltage. A voltage compensation unit outputs a compensation reference voltage by controlling the reference voltage in accordance with the output value of the sense amplifier. | 03-31-2011 |
| 20110143477 | METHOD OF MANUFACTURING A PHASE CHANGE MEMORY DEVICE USING A CROSS PATTERNING TECHNIQUE - A method of manufacturing a phase change memory device is provided. A first insulating layer having a plurality of metal word lines spaced apart at a constant distance is formed on a semiconductor substrate. A plurality of line structures having a barrier metal layer, a polysilicon layer and a hard mask layer are formed to be overlaid on the plurality of metal word lines. A second insulating layer is formed between the line structures. Cross patterns are formed by etching the hard mask layers and the polysilicon layers of the line structures using mask patterns crossed with the metal word lines. A third insulating layer is buried within spaces between the cross patterns. Self-aligned phase change contact holes are formed and at the same time, diode patterns formed of remnant polysilicon layers are formed by selectively removing the hard mask layers constituting the cross patterns. | 06-16-2011 |
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| 20090137080 | PHASE CHANGE MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device reduces the current necessary to cause a phase change of a phase change layer. The phase change memory device includes a first oxide layer formed on a semiconductor substrate; a lower electrode formed inside the first oxide layer; a second oxide layer formed on the first oxide layer including the lower electrode, the second oxide having a hole for exposing a part of the lower electrode; a phase change layer formed on a surface of the hole with a uniform thickness so as to make contact with the lower electrode; and an upper electrode formed in the hole and on a part of the second oxide layer, the part being adjacent to the hole. | 05-28-2009 |
| 20090137081 | PHASE CHANGE RAM DEVICE AND METHOD FOR MANUFACTURING THE SAME - A phase change RAM device includes a semiconductor substrate having a phase change cell area and a voltage application area; a first oxide layer, a nitride layer and a second oxide layer sequentially formed on the semiconductor substrate; a first plug formed in the first oxide layer, the nitride layer and the second oxide layer of the phase change cell area; a second plug formed in the first oxide layer and the nitride layer of the voltage application area; a conductive line formed in the second oxide layer; a third oxide layer formed on the second oxide layer; a lower electrode shaped like a plug, the lower electrode being formed so as to directly make contact with the first plug; and a phase change layer and an upper electrode sequentially formed on the lower electrode in a pattern form. | 05-28-2009 |
| 20090231899 | PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME - A phase change random access memory (PRAM) includes a cell array divided into an active region and a dummy active region. A bitline is formed across the active region and the dummy active region and a global wordline is formed in the active region so as to intersect with the bitline. The cell array includes a phase change memory cell formed at an intersection point of the bitline and the global wordline that is electrically connected with the bitline and the global wordline. The cell array further includes a phase change dummy cell formed below the bitline in the dummy active region that is electrically isolated from the bitline. The dummy cell maintains a turn-off state as the dummy cell and the bitline are electrically isolated from each other. | 09-17-2009 |
| 20100127234 | PHASE CHANGE MEMORY DEVICE HAVING AN INCREASED SENSING MARGIN FOR CELL EFFICIENCY AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device having an increased sensing margin for improved cell efficiency. The phase change memory device includes a plurality of diodes formed in an active region of a semiconductor substrate; an insulation layer pattern formed on the respective diodes; a phase change layer formed on the insulation layer pattern in such a way as not to be electrically connected with the diodes; bit lines formed over the phase change layer; and a global X-decoder line formed over the bit lines. The present invention suppresses current flow in a phase change memory device because the dummy cell string and the dummy active region are not electrically connected with each other under the global X-decoder line, whereby preventing parasitic current from being produced in the phase change memory device. | 05-27-2010 |
| 20100252831 | SQUARE PILLAR-SHAPED SWITCHING ELEMENT FOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A switching element for a memory device includes a base layer including a plurality of line-type trenches. First insulation patterns are formed on the base layer excluding the trenches. First diode portions are formed on the bottoms of the trenches in the form of a thin film. Second insulation patterns are formed on the first diode portions and are spaced apart from each other to form holes in the trenches having the first diode portions provided therein. Square pillar-shaped second diode portions are formed in the holes over the first diode portions. | 10-07-2010 |
| 20110053317 | PHASE CHANGE RAM DEVICE AND METHOD FOR FABRICATING THE SAME - Disclosed are a phase change RAM device and a method for fabricating a phase change RAM device, which can efficiently lower intensity of current required for changing a phase of a phase change layer. The method includes the steps of providing a semiconductor substrate formed with an insulating interlayer including a tungsten plug, forming a first oxide layer on the semiconductor substrate, forming a pad-type bottom electrode, which makes contact with the tungsten plug, in the first oxide layer, forming a second oxide layer on the first oxide layer including the bottom electrode, and forming a porous polystyrene pattern on the second oxide layer such that a predetermined portion of the second oxide layer corresponding to a center portion of the bottom electrode is covered with the porous polystyrene pattern. | 03-03-2011 |
