Patent application number | Description | Published |
20090248927 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has take place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. | 10-01-2009 |
20090248936 | CHIP INTERCONNECT SWIZZLE MECHANISM - A front side bus swizzle mechanism modifies the front side (address and data) bus on a chip so that, when the chip is positioned on one side of a printed circuit board, connection to a second chip located on the opposite side of the printed circuit board is simplified. The simplified connection may result in less complexity and minimize the consumption of additional printed circuit board real estate. | 10-01-2009 |
20140108684 | INTERCONNECT BANDWIDTH THROTTLER - An interconnect bandwidth throttler is disclosed. The interconnect bandwidth throttler turns off the interconnect, based on whether a maximum number of transactions has taken place within a predetermined throttle window. Both the maximum number of transactions and the throttle window are adjustable. Characteristics such as performance, thermal considerations, and average power are adjustable using the interconnect bandwidth throttler. | 04-17-2014 |
20140149999 | Technique for Monitoring Activity within an Integrated Circuit - A technique to monitor events within a computer system or integrated circuit. In one embodiment, a software-accessible event monitoring storage and hardware-specific monitoring logic are selectable and their corresponding outputs may be monitored by accessing a counter to count events corresponding to each of software-accessible storage and hardware-specific monitoring logic. | 05-29-2014 |
Patent application number | Description | Published |
20090172429 | POWER MODE CONTROL METHOD AND CIRCUITRY - In some embodiments, a power up (or power mode) interface is provided whereby a chip's power up signals are encoded into multiple states to provide more functions than the number of signals used to define the states. | 07-02-2009 |
20100332686 | WRITE COMBINING PROTOCOL BETWEEN PROCESSORS AND CHIPSETS - Systems and methods of processing write transactions provide for combining write transactions on an input/output (I/O) hub according to a protocol between the I/O hub and a processor. Data associated with the write transactions can be flushed to an I/O device without the need for proprietary software and specialized registers within the I/O device. | 12-30-2010 |
20110145909 | Interface Logic For A Multi-Core System-On-A-Chip (SoC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 06-16-2011 |
20120243364 | METHOD AND SYSTEM FOR DYNAMIC POWER MANAGEMENT OF MEMORIES - A method and apparatus for dynamic power management of memories. In one embodiment of the invention, the power consumption of the memories is reduced based on the operating state of the memories. For example, in one embodiment of the invention, the power supply to the memories is reduced when the memories are in an inactive state by reducing and/or turning off the input voltage(s) to the memories. In one embodiment of the invention, the processing unit dynamically changes the strength of the On-Die Termination pull-up/pull-down resistance based on the memory operating mode, memory voltage, and memory temperature. | 09-27-2012 |
20140108695 | INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 04-17-2014 |