| Patent application number | Description | Published |
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| 20080203408 | PROCESS FOR PRODUCING (Al, Ga)lnN CRYSTALS - The present invention relates to a novel process for producing (Al, Ga)InN and AlGaInN single crystals by means of a modified HVPE process, and also to (Al, Ga)InN and AlGaInN bulk crystals of high quality, in particular homogeneity. | 08-28-2008 |
| 20080203409 | PROCESS FOR PRODUCING (Al, Ga)N CRYSTALS - The present invention relates to a novel process for producing (Al, Ga)N and AlGaN single crystals by means of a modified HVPE process, and also to (Al, Ga)N and AlGaN single crystals of high quality. | 08-28-2008 |
| 20080213543 | Method and device for manufacturing semiconductor compound materials by means of vapour phase epitaxy - A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor. | 09-04-2008 |
| 20110018106 | METHOD FOR PRODUCING III-N LAYERS, AND III-N LAYERS OR III-N SUBSTRATES, AND DEVICES BASED THEREON - An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed. | 01-27-2011 |
| 20120021163 | METHOD AND DEVICE FOR MANUFACTURING SEMICONDUCTOR COMPOUND MATERIALS BY MEANS OF VAPOUR PHASE EPITAXY - A semiconductor compound material, preferably a III-N-bulk crystal or a III-N-layer, is manufactured in a reactor by means of hydride vapour phase epitaxy (HVPE), wherein in a mixture of carrier gases a flow profile represented by local mass flow rates is formed in the reactor. The mixture can carry one or more reaction gases towards a substrate. Thereby, a concentration of hydrogen important for the reaction and deposition of reaction gases is adjusted at the substrate surface independently from the flow profile simultaneously formed in the reactor. | 01-26-2012 |
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| 20080216035 | METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS - A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data. | 09-04-2008 |
| 20080250283 | POWER SAVING FLIP-FLOP - A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled. | 10-09-2008 |
| 20080258700 | METHOD AND APPARATUS FOR ADJUSTING ON-CHIP DELAY WITH POWER SUPPLY CONTROL - An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency. | 10-23-2008 |
| 20090134912 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 05-28-2009 |
| 20100153824 | SOFT-ERROR DETECTION FOR ELECTRONIC-CIRCUIT REGISTERS - In one embodiment, a circuit has multiple flip-flops with gated clock inputs controlled by an enable signal, where the clock signal is gated in order to reduce power consumption by the circuit. The circuit has an error detection and correction (EDC) module that is active when the enable signal is low in order to detect and correct soft errors of the flip-flops. The EDC module generates and stores an error-correction code based on the data outputs of the flip-flops. The EDC module then compares the stored error-correction code to a presently generated error-correction code, where if they are not identical, then the EDC (a) determines (i) that a soft error has occurred and (ii) which flip-flop suffered the soft error and (b) flips a corresponding error-correction signal to provide a correct corresponding output signal while the enable signal is low. | 06-17-2010 |
| 20110066905 | Test Pin Gating for Dynamic Optimization - An improvement to an integrated circuit of a type having a test enable line for enabling an electrical test of the integrated circuit only when the test enable line is at a logical high value, and output lines that are only used during the electrical test of the integrated circuit, where the improvement is a switch circuit for disabling a state change in the output lines when the test enable line is at a logical low value. In this manner, the output lines do not switch during functional use of the integrated circuit, and cannot be aggressors on the data signals that are carried by the data lines that are used during the functional use of the integrated circuit. In addition, these non-switching output lines can act as guard traces that run between the data lines, further electrically isolating the data lines from one another. Further, because they do not switch during functional use of the integrated circuit, the overall power consumption of the integrated circuit is reduced. | 03-17-2011 |
| 20110084726 | ADJUSTABLE HOLD FLIP FLOP AND METHOD FOR ADJUSTING HOLD REQUIREMENTS - A method and apparatus are provided for storing a value in a process register of an electrical circuit, which indicates a strength of a process in which the circuit was fabricated, and adjusting an input delay applied to data signals received by a synchronous storage element of the electrical circuit based on the stored value. | 04-14-2011 |
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| 20110035185 | Sensor-based Tracking of Variable Locomotion - The invention relates to a method, device and system for the sensor-based tracking of a variable locomotion, and, in particular, to a method, device and system for acceleration-sensor based measurement of the highly erratic movement of a team sports player. The method comprises continuously measuring acceleration values corresponding to the locomotion of a person. For a single step of the person, a type of locomotion is determined by analyzing a temporal sequence of acceleration values of a portion of the acceleration values corresponding to the single step. Further, a swing time and at least one characterizing acceleration value are determined from the acceleration values for the single step and the step length is determined based on the type of locomotion, the swing time and the at least one characterizing acceleration value. | 02-10-2011 |
| 20110156868 | SYSTEM UND VERFAHREN ZUR AUTOMATISIERTEN ANALYSE EINES WETTKAMPFVERLAUFES - System, consisting of at least one active or passive position detection system which sends data about the position of at least one athlete to a central evaluation unit; and a central evaluation unit which stores received positional data in a database, automatically calculates a movement pattern consisting of at least the covered distance and the mean velocity from the positional data, and represents the movement pattern on a display. | 06-30-2011 |
| 20110175744 | Systems and Method for the Mobile Evaluation of Cushioning Properties of Shoes - Shoe having at least one pressure sensor provided in the shoe cushioning element, as well as system components for emitting, receiving and evaluating the signals of the sensor. | 07-21-2011 |
