| Patent application number | Description | Published |
|---|
| 20090119358 | Computational method, system, and apparatus - A method, system, and apparatus for performing computations. | 05-07-2009 |
| 20090292843 | Controlling passthrough of communications between multiple buses - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 11-26-2009 |
| 20100009640 | Digital Architecture Using One-Time Programmable (OTP) Memory - In one aspect, the present invention includes an apparatus having a digital signal processor (DSP), a controller coupled to the DSP to provide control signals to the DSP, and a one-time programmable (OTP) memory coupled to the DSP and the controller. The OTP memory may include multiple code portions including a first code block to control the DSP and a second code block to control the controller. | 01-14-2010 |
| 20110099310 | CONTROLLING PASSTHROUGH OF COMMUNICATION BETWEEN MULTIPLE BUSES - A demodulator can include first data and clock pads to couple the demodulator to a host device via a first bus, and second data and clock pads to couple the demodulator to a radio frequency (RF) tuner via a second bus. The device may further include passthrough logic to couple host data and a host clock from the first bus to the second bus and to couple tuner data from the second bus to the first bus during a passthrough mode. During this mode, however, the two buses may remain electrically decoupled. When the passthrough mode is disabled, the RF tuner is thus shielded from noise present on the first bus. | 04-28-2011 |
| Patent application number | Description | Published |
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| 20110115537 | CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL - Embodiments include circuit devices and methods for re-clocking an input signal. In an embodiment, a circuit device includes a data storage element having a data input to receive a digital data stream having a first clock rate and including a clock input to receive a clock signal having a second clock rate. The data storage element further includes logic to adjust edge timing of transitions within the digital data stream based on the clock signal to produce a modulated output signal having a power spectrum with spectral nulls at a desired frequency and its harmonics without changing an average data rate. | 05-19-2011 |
| 20110158298 | TUNER CIRCUIT WITH AN INTER-CHIP TRANSMITTER AND METHOD OF PROVIDING AN INTER-CHIP LINK FRAME - A tuner circuit includes a digital signal processor to generate a digital data stream related to a radio frequency signal and a transceiver circuit coupled to the digital signal processor and configurable to generate an inter-chip communication frame having a start portion and a plurality of channels. The plurality of channels includes a first data channel to carry a portion of the digital data stream and a control channel to carry control data. The transceiver circuit is configurable to send the inter-chip communication frame to an additional tuner circuit through an inter-chip communication link. | 06-30-2011 |
| 20110158339 | ANTENNA DIVERSITY SYSTEM WITH MULTIPLE TUNER CIRCUITS HAVING MULTIPLE OPERATING MODES AND METHODS - In an embodiment, a tuner circuit includes an inter-chip receiver circuit configurable to couple to a first inter-chip communication link to receive a first data stream and includes an analog-to-digital converter configured to convert a radio frequency signal into a digital version of the radio frequency signal. The tuner circuit further includes a digital signal processor coupled to the inter-chip receiver circuit and the analog-to-digital converter. The digital signal processor is configurable to generate an output signal related to at least one of the first data stream and the digital version of the radio frequency signal based on a selected operating mode. | 06-30-2011 |
| 20110158357 | ANTENNA DIVERSITY SYSTEM WITH FRAME SYNCHRONIZATION - In an embodiment, a tuner circuit includes circuitry to produce a first DSP frame based on a first RF signal and includes an inter-chip receiver circuit coupled to an inter-chip link and configured to receive an inter-chip frame. The inter-chip receiver circuit is configured to detect a start of frame symbol of the inter-chip frame and to extract a DSP offset and data related to a second DSP frame from the inter-chip frame. The tuner circuit further includes a digital signal processor coupled to the circuitry and to the inter-chip receiver circuit. The digital signal processor is to synchronize the first DSP frame with the second DSP frame based on the start of frame symbol and the digital signal processor offset, the digital signal processor configured to perform a selected antenna diversity operation on the first and second DSP frames to produce an output signal. | 06-30-2011 |
