| Patent application number | Description | Published |
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| 20090166853 | MULTI-LAYER STACKED WAFER LEVEL SEMICONDUCTOR PACKAGE MODULE - A stacked wafer level semiconductor package module includes a semiconductor chip module including first and second semiconductor chips each having a rectangular shape. The first semiconductor chip has first pads disposed along a first short side of a lower surface thereof. The second semiconductor chip has second pads disposed along a first short side of a lower surface thereof. The first and second semiconductor chips are stacked so as to expose the first pad and the second pad on one side of the stacked first and second semiconductor chips. The package also includes a substrate having a first connection pad facing the first pad and a second connection pad facing the second pad. The package also includes a first connection member for connecting the first pad to the first connection pad, and a second connection member for connecting the second pad to the second connection pad. | 07-02-2009 |
| 20090184414 | WAFER LEVEL CHIP SCALE PACKAGE HAVING AN ENHANCED HEAT EXCHANGE EFFICIENCY WITH AN EMF SHIELD AND A METHOD FOR FABRICATING THE SAME - A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads. | 07-23-2009 |
| 20090189267 | SEMICONDUCTOR CHIP WITH CHIP SELECTION STRUCTURE AND STACKED SEMICONDUCTOR PACKAGE HAVING THE SAME - A semiconductor chip with a chip selection structure suitable for a stacked semiconductor chip includes a semiconductor chip body and a chip selection structure. The chip selection structure includes a chip selection pad disposed over the semiconductor chip body, a main through electrode electrically connected to the chip selection pad, and a sub through electrode interposed between the main through electrode and the chip selection pad. A plurality of the semiconductor chips, each having the same chip selection structure, can be stacked by offsetting the stacked semiconductor chips. | 07-30-2009 |
| 20090197372 | METHOD FOR MANUFACTURING STACK PACKAGE USING THROUGH-ELECTRODES - Manufacturing a wafer level stack package includes the steps of back-grinding a lower surface of a wafer including a plurality of first semiconductor chips. A support member is attached to a lower surface of the back-grinded wafer. One or more second semiconductor chips are stacked on the respective first semiconductor chips of the back-grinded wafer. First through-electrodes are formed to electrically connect the stacked first semiconductor chips and second semiconductor chips. Third semiconductor chips are attached to uppermost ones of the stacked second semiconductor chips, and the third semiconductor chips have second through-electrodes which are electrically connected to the first through-electrodes and re-distribution lines which are connected to the second through-electrodes. Outside connection terminals are attached to the re-distribution lines of the third semiconductor chips. The first semiconductor chips of a wafer level on which the second and third semiconductor chips are stacked are sawed to for semiconductor packages at a chip level. | 08-06-2009 |
| Patent application number | Description | Published |
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| 20110086292 | JOINING DEVICE FOR FUEL CELL STACK AND FUEL CELL STACK PROVIDED WITH THE SAME - The present invention features a fuel cell stack that preferably includes an electricity generating assembly having a plurality of unit cells that are suitably disposed one after another; a pair of end plates pressedly disposed respectively at upper and lower ends of the electricity generating assembly; and a joining device suitably engaging the end plates by a rope, where pressure is applied to the electricity generating assembly by means of tension of the rope, and the length and tension of the rope is suitably controlled. | 04-14-2011 |
| 20110129737 | COMPOSITE SEPARATOR FOR POLYMER ELECTROLYTE MEMBRANE FUEL CELL AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a composite separator for a polymer electrolyte membrane fuel cell (PEMFC) and a method for manufacturing the same, in which a graphite foil prepared by compressing expanded graphite is stacked on a carbon fiber-reinforced composite prepreg or a mixed solution prepared by mixing graphite flake and powder with a resin solvent is applied to the cured composite prepreg such that a graphite layer is integrally molded on the outermost end of the separator. | 06-02-2011 |
| 20110281203 | METHOD FOR MANUFACTURING COMPOSITE SEPARATOR FOR FUEL CELL AND COMPOSITE SEPARATOR MANUFACTURED BY THE SAME - The present invention provides a method for manufacturing a composite separator for a fuel cell, which can reduce the electrical contact resistance by performing an additional post-treatment to remove residual resin remaining on the surface of the composite separator by plasma etching. In certain preferred embodiments, the present invention provides a method for manufacturing a composite separator for a fuel cell, in which a liquid phase resin for gasket is applied to the surface of the composite separator along a predetermined gasket pattern, or a semi-cured resin for gasket in the form of a film with a predetermined gasket pattern is stacked on the surface of the composite separator, and then plasma etching is performed to remove the residual resin and, at the same time, cure the resin for gasket, thus reducing the overall processing time to improve the productivity and preventing a composite material of the separator from being damaged. | 11-17-2011 |
