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Ha-Jin
Ha Jin Hwang, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20100119675 | DOUGHNUT MAKING METHOD USING SOYBEAN POWDER - A doughnut making method comprises: pulverizing beans to bean powder using an airflow crushing technique; mixing flour, baking powder and whole milk powder to the bean powder to form a first mixture; mixing the first mixture to a second mixture to form a third mixture, wherein the second mixture is formed of refined sugar, salt and margarine; sieving the third mixture to form a premix; admixing water and egg mix to the premix and pasting the admixture to a dough; and frying the dough in oil to form doughnuts. | 05-13-2010 |
Ha Jin Jeong, Gwangju-City KR
| Patent application number | Description | Published |
|---|---|---|
| 20110094726 | Refrigerator and control method of the same - A refrigerator having a valve to control the supply of a refrigerant to a plurality of storage chambers and a control method of the same. An opening time rate of the valve is changed based on modes of the storage chambers to control the amount of the refrigerant supplied to the storage chambers, thereby avoiding concentration of the refrigerant in one of the storage chambers and thus preventing refrigerant shortage in the other storage chambers. Also, left and right temperature deviation of each storage chamber is reduced, thereby achieving uniform temperature distribution of each storage chamber. | 04-28-2011 |
Ha Jin Lee, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20110294660 | REUSABLE HEAVY METAL REMOVER AND FABRICATION METHOD THEREOF - A heavy metal remover of a core-shell structure comprises a core including carbon nanotubes (CNT) that can aggregate and scatter in a reversible manner, and a shell including iron oxide. A method for fabricating a heavy metal remover of a core-shell structure comprises (a) preparing a carbon nanotube (CNT) aqueous solution where acid-treated CNTs have dissolved, (b) mixing the CNT aqueous solution with an aqueous solution of polymer template particles, thereby forming a CNT layer on the surface of the template particles, (c) mixing the solution having undergone the step (b) with a polymer electrolyte having positive charges, thereby forming a polymer layer on an outer surface of the CNT layer, (d) adding FeSO | 12-01-2011 |
Ha-Jin Jeong, Gwangsan-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20100139300 | Refrigeration and control method thereof - Disclosed is a refrigerator includes a storage room and having a cool air off mode in which supply of cool air to the storage room is cut off. Thus, a refrigerator having a cooling system in which a pair of evaporators are serially connected for a pair of storage rooms is provided according to the above embodiments. A refrigerator may also have a cooling system in which a plurality of evaporators is connected in parallel and refrigerant is selectively supplied to each evaporator by a refrigerant supply valve. | 06-10-2010 |
Ha-Jin Kim, Yongin-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20080211101 | Interlayer wiring of semiconductor device using carbon nanotube and method of manufacturing the same - Provided is an interlayer wiring structure of a semiconductor device using carbon nanotubes, and a method of manufacturing the interlayer wiring structure. The interlayer wiring structure is a carbon nanotube bundle that connects a first electrode to a second electrode. The carbon nanotube bundle includes a plurality of carbon nanotubes grown from a catalyst layer that is formed on a first electrode. The carbon nanotube bundle is made in a manner that a portion of the carbon nanotube bundle close to the second electrode has higher density of carbon nanotubes than another portion of the carbon nanotube bundle close to the first electrode. The carbon nanotube bundle is surrounded by an interlayer dielectric. In one embodiment of a method of manufacturing the carbon nanotube interlayer wire, liquid droplets are distributed between the carbon nanotubes to induce surface tension between the carbon nanotubes. The surface tension makes the carbon nanotube bundle maintain higher density of carbon nanotubes in a portion close to the second electrode. | 09-04-2008 |
| 20100074834 | APPARATUS AND METHOD FOR SURFACE-TREATING CARBON FIBER BY RESISTIVE HEATING - In an apparatus for surface-treating a carbon fiber, wherein the carbon fiber is heated by resistive heating, a carbon-containing gas is disposed on the carbon fiber, and carbon nanotubes are grown on a surface of the carbon fiber. | 03-25-2010 |
Ha-Jin Kim, Hwaseong-Si KR
| Patent application number | Description | Published |
|---|---|---|
| 20110044739 | FUSING DEVICE INCLUDING RESISTIVE HEATING LAYER AND IMAGE FORMING APPARATUS INCLUDING THE FUSING DEVICE - A fusing device includes; a heating member having a resistive heating layer constituting an outermost portion of the heating member, a nip forming member facing the heating member to form a fusing nip therewith, and a plurality of current supplying electrodes which contact an outer circumference of the resistive heating layer to supply electrical current to the resistive heating layer. | 02-24-2011 |
| 20110116850 | HEATING MEMBER INCLUDING RESISTIVE HEATING LAYER, AND FUSING APPARATUS AND IMAGE FORMING APPARATUS INCLUDING THE HEATING MEMBER - A heating member includes a resistive heating layer disposed on an outermost layer of the heating member, where the resistive heating layer comprises a conductive filler distributed in a base material and where the resistive heating layer emits heat when supplied with an electric current from an electrode, and a contacting unit which exposes the conductive filler of the resistive heating layer and contacts the electrode.. | 05-19-2011 |
Ha-Jin Lim, Gwangjin-Gu KR
| Patent application number | Description | Published |
|---|---|---|
| 20110193181 | SEMICONDUCTOR DEVICE HAVING DIFFERENT METAL GATE STRUCTURES - A semiconductor includes a channel region in a semiconductor substrate, a gate dielectric film on the channel region, and a gate on the gate dielectric film. The gate includes a doped metal nitride film, formed from a nitride of a first metal and doped with a second metal which is different from the first metal, and a conductive polysilicon layer formed on the doped metal nitride film. The gate may further include a metal containing capping layer interposed between the doped metal nitride film and the conductive polysilicon layer. | 08-11-2011 |
Ha-Jin Lim, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080261360 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, a gate insulation layer is formed on a substrate including a first channel of a first conductive type and a second channel of a second conductive type different from the first conductive type. A first conductive layer including a first metal is formed on the gate insulation layer, and a second conductive layer including a second metal different from the first metal is formed on the first conductive layer formed over the second channel. The second conductive layer is partially removed by a wet etching process to form a second conductive layer pattern over the second channel. | 10-23-2008 |
| 20090283764 | TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME - Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer. | 11-19-2009 |
| 20090291568 | Semiconductor devices and method of forming the same - Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer. | 11-26-2009 |
| 20100025781 | Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film. | 02-04-2010 |
| 20100167533 | METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer. | 07-01-2010 |
| 20100171182 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING SELECTIVE STRESS RELAXATION OF ETCH STOP LAYER - A strained semiconductor device includes a first plurality of transistors spaced with a first gate pitch, a second plurality of transistors spaced with a second gate pitch greater than the first gate pitch, and an etch stop layer disposed on the first and second pluralities of transistors. The etch stop layer between each of the second plurality of transistors has a greater proportion of a stress-altering material than the etch stop layer between each of the first plurality of transistors. | 07-08-2010 |
| 20110018044 | ETCH STOP LAYERS AND METHODS OF FORMING THE SAME - A semiconductor device includes a MOSFET, and a plurality of stress layers disposed on the MOSFET, wherein the stress layers include a first stress layer disposed on the MOSFET and a second stress layer disposed on the first stress layer, the first stress layer has a first stress and the second stress layer has a second stress, and the first stress is different from the second stress. | 01-27-2011 |
| 20110287622 | Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film. | 11-24-2011 |
Ha-Jin Yoo, Seoul KR
| Patent application number | Description | Published |
|---|---|---|
| 20080249774 | METHOD AND APPARATUS FOR SPEECH SPEAKER RECOGNITION - Disclosed is a method for speech speaker recognition of a speech speaker recognition apparatus, the method including detecting effective speech data from input speech; extracting an acoustic feature from the speech data; generating an acoustic feature transformation matrix from the speech data according to each of Principal Component Analysis (PCA) and Linear Discriminant Analysis (LDA), mixing each of the acoustic feature transformation matrixes to construct a hybrid acoustic feature transformation matrix, and multiplying the matrix representing the acoustic feature with the hybrid acoustic feature transformation matrix to generate a final feature vector; and generating a speaker model from the final feature vector, comparing a pre-stored universal speaker model with the generated speaker model to identify the speaker, and verifying the identified speaker. | 10-09-2008 |